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| author | Jim Grosbach <grosbach@apple.com> | 2010-06-02 21:53:11 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-06-02 21:53:11 +0000 |
| commit | 18f30e6f5e80787808fe1455742452a5210afe07 (patch) | |
| tree | 25fb6cc56404594f8d8c6ed5057e6f9cd3a462c7 /lib/Target/ARM/ARMLoadStoreOptimizer.cpp | |
| parent | 7c8c8830a950a5cc0ddc6d463a205d88cfeb9620 (diff) | |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 8585c1e501..847ea925b8 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -968,8 +968,8 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, Pred, PredReg, TII, isT2); } else { if (OddReg == EvenReg && EvenDeadKill) { - // If the two source operands are the same, the kill marker is probably - // on the first one. e.g. + // If the two source operands are the same, the kill marker is + // probably on the first one. e.g. // t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0 EvenDeadKill = false; OddDeadKill = true; |