diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-02-22 19:53:14 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-02-22 19:53:14 +0000 |
| commit | 6557bce3ec8d5a82b2ea299a18cb51677b299633 (patch) | |
| tree | 8cb296c4fb21b11e13d819b58b36f2c4cd7cd655 /lib/Target/ARM/ARMHazardRecognizer.cpp | |
| parent | 50d280c14ee1c25fc8e6cb6f59af44f754edce42 (diff) | |
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126238 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMHazardRecognizer.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMHazardRecognizer.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMHazardRecognizer.cpp b/lib/Target/ARM/ARMHazardRecognizer.cpp index 676b01e91c..e97ce50bc4 100644 --- a/lib/Target/ARM/ARMHazardRecognizer.cpp +++ b/lib/Target/ARM/ARMHazardRecognizer.cpp @@ -21,17 +21,14 @@ static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, // FIXME: Detect integer instructions properly. const TargetInstrDesc &TID = MI->getDesc(); unsigned Domain = TID.TSFlags & ARMII::DomainMask; - if (Domain == ARMII::DomainVFP) { - unsigned Opcode = MI->getOpcode(); - if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD || - Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) - return false; - } else if (Domain == ARMII::DomainNEON) { - if (MI->getDesc().mayStore() || MI->getDesc().mayLoad()) - return false; - } else + if (TID.mayStore()) return false; - return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); + unsigned Opcode = TID.getOpcode(); + if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) + return false; + if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON)) + return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); + return false; } ScheduleHazardRecognizer::HazardType |