diff options
| author | Andrew Trick <atrick@apple.com> | 2012-10-11 05:37:06 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-11 05:37:06 +0000 |
| commit | 4903c15b7d92802a4f0f28928a89bb4c0d5e212f (patch) | |
| tree | e7e0717dabf441ae68c8e454639a855f86542dcd /lib/CodeGen/TargetInstrInfoImpl.cpp | |
| parent | 5e01f80bf85b9a68352d4c146caa9ddcf6af6dcf (diff) | |
misched: Handle "transient" non-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetInstrInfoImpl.cpp')
| -rw-r--r-- | lib/CodeGen/TargetInstrInfoImpl.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index 8ed66f7044..4439192fe2 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -563,6 +563,8 @@ TargetInstrInfoImpl::getNumMicroOps(const InstrItineraryData *ItinData, /// Return the default expected latency for a def based on it's opcode. unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, const MachineInstr *DefMI) const { + if (DefMI->isTransient()) + return 0; if (DefMI->mayLoad()) return SchedModel->LoadLatency; if (isHighLatencyDef(DefMI->getOpcode())) |