llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8

16 files changed, 106 insertions, 106 deletions

diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index 9289711e6e..2f4db28d64 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -67,11 +67,11 @@ void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
     ISD::ArgFlagsTy ArgFlags =
       cast<ARG_FLAGSSDNode>(TheArgs->getOperand(3+i))->getArgFlags();
     if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-      std::string msg;
-      raw_string_ostream Msg(msg);
-      Msg << "Formal argument #" << i << " has unhandled type "
+#ifndef NDEBUG
+      cerr << "Formal argument #" << i << " has unhandled type "
            << ArgVT.getMVTString();
-      llvm_report_error(Msg.str());
+#endif
+      llvm_unreachable(0);
     }
   }
 }
@@ -84,12 +84,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
     MVT VT = TheRet->getOperand(i*2+1).getValueType();
     ISD::ArgFlagsTy ArgFlags =
       cast<ARG_FLAGSSDNode>(TheRet->getOperand(i*2+2))->getArgFlags();
-    if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
-      std::string msg;
-      raw_string_ostream Msg(msg);
-      Msg << "Return operand #" << i << " has unhandled type "
+    if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
+#ifndef NDEBUG
+      cerr << "Return operand #" << i << " has unhandled type "
            << VT.getMVTString();
-      llvm_report_error(Msg.str());
+#endif
+      llvm_unreachable(0);
     }
   }
 }
@@ -103,11 +103,11 @@ void CCState::AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn) {
     MVT ArgVT = TheCall->getArg(i).getValueType();
     ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
     if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-      std::string msg;
-      raw_string_ostream Msg(msg);
-      Msg << "Call operand #" << i << " has unhandled type "
+#ifndef NDEBUG
+      cerr << "Call operand #" << i << " has unhandled type "
            << ArgVT.getMVTString();
-      llvm_report_error(Msg.str());
+#endif
+      llvm_unreachable(0);
     }
   }
 }
@@ -122,11 +122,11 @@ void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
     MVT ArgVT = ArgVTs[i];
     ISD::ArgFlagsTy ArgFlags = Flags[i];
     if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-      std::string msg;
-      raw_string_ostream Msg(msg);
-      Msg << "Call operand #" << i << " has unhandled type "
+#ifndef NDEBUG
+      cerr << "Call operand #" << i << " has unhandled type "
            << ArgVT.getMVTString();
-      llvm_report_error(Msg.str());
+#endif
+      llvm_unreachable(0);
     }
   }
 }
@@ -140,11 +140,11 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) {
     if (TheCall->isInreg())
       Flags.setInReg();
     if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
-      std::string msg;
-      raw_string_ostream Msg(msg);
-      Msg << "Call result #" << i << " has unhandled type "
+#ifndef NDEBUG
+      cerr << "Call result #" << i << " has unhandled type "
            << VT.getMVTString();
-      llvm_report_error(Msg.str());
+#endif
+      llvm_unreachable(0);
     }
   }
 }
@@ -153,10 +153,10 @@ void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) {
 /// produce a single value.
 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
   if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
-    std::string msg;
-    raw_string_ostream Msg(msg);
-    Msg << "Call result has unhandled type "
+#ifndef NDEBUG
+    cerr << "Call result has unhandled type "
          << VT.getMVTString();
-    llvm_report_error(Msg.str());
+#endif
+    llvm_unreachable(0);
   }
 }
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7f233b219b..632c9fd09d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -393,7 +393,7 @@ static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
 
   assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
   switch (Op.getOpcode()) {
-  default: LLVM_UNREACHABLE("Unknown code");
+  default: llvm_unreachable("Unknown code");
   case ISD::ConstantFP: {
     APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
     V.changeSign();
@@ -2259,7 +2259,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
       switch (N0.getOpcode()) {
       default:
-        LLVM_UNREACHABLE("Unhandled SetCC Equivalent!");
+        llvm_unreachable("Unhandled SetCC Equivalent!");
       case ISD::SETCC:
         return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
       case ISD::SELECT_CC:
@@ -5063,7 +5063,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
     if (Value.getOpcode() != ISD::TargetConstantFP) {
       SDValue Tmp;
       switch (CFP->getValueType(0).getSimpleVT()) {
-      default: LLVM_UNREACHABLE("Unknown FP type");
+      default: llvm_unreachable("Unknown FP type");
       case MVT::f80:    // We don't do this for these yet.
       case MVT::f128:
       case MVT::ppcf128:
@@ -6107,7 +6107,7 @@ bool DAGCombiner::FindAliasInfo(SDNode *N,
     SrcValue = ST->getSrcValue();
     SrcValueOffset = ST->getSrcValueOffset();
   } else {
-    LLVM_UNREACHABLE("FindAliasInfo expected a memory operand");
+    llvm_unreachable("FindAliasInfo expected a memory operand");
   }
 
   return false;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index a40a0c3ab6..01f3cc7af1 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -949,7 +949,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 #ifndef NDEBUG
     cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to legalize this operator!");
+    llvm_unreachable("Do not know how to legalize this operator!");
   case ISD::CALL:
     // The only option for this is to custom lower it.
     Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
@@ -983,7 +983,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     return Tmp2;
   case ISD::BUILD_VECTOR:
     switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
-    default: LLVM_UNREACHABLE("This action is not supported yet!");
+    default: llvm_unreachable("This action is not supported yet!");
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
       if (Tmp3.getNode()) {
@@ -1100,7 +1100,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp4 = Result.getValue(1);
 
       switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
-      default: LLVM_UNREACHABLE("This action is not supported yet!");
+      default: llvm_unreachable("This action is not supported yet!");
       case TargetLowering::Legal:
         // If this is an unaligned load and the target doesn't support it,
         // expand it.
@@ -1270,7 +1270,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         Tmp2 = LegalizeOp(Ch);
       } else {
         switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
-        default: LLVM_UNREACHABLE("This action is not supported yet!");
+        default: llvm_unreachable("This action is not supported yet!");
         case TargetLowering::Custom:
           isCustom = true;
           // FALLTHROUGH
@@ -1363,7 +1363,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
         MVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
-        default: LLVM_UNREACHABLE("This action is not supported yet!");
+        default: llvm_unreachable("This action is not supported yet!");
         case TargetLowering::Legal:
           // If this is an unaligned store and the target doesn't support it,
           // expand it.
@@ -1463,7 +1463,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
                                           ST->getOffset());
 
         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
-        default: LLVM_UNREACHABLE("This action is not supported yet!");
+        default: llvm_unreachable("This action is not supported yet!");
         case TargetLowering::Legal:
           // If this is an unaligned store and the target doesn't support it,
           // expand it.
@@ -1691,7 +1691,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
   MVT OpVT = LHS.getValueType();
   ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
   switch (TLI.getCondCodeAction(CCCode, OpVT)) {
-  default: LLVM_UNREACHABLE("Unknown condition code action!");
+  default: llvm_unreachable("Unknown condition code action!");
   case TargetLowering::Legal:
     // Nothing to do.
     break;
@@ -1699,7 +1699,7 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
     ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
     unsigned Opc = 0;
     switch (CCCode) {
-    default: LLVM_UNREACHABLE("Don't know how to expand this condition!");
+    default: llvm_unreachable("Don't know how to expand this condition!");
     case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO;  Opc = ISD::AND; break;
     case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO;  Opc = ISD::AND; break;
     case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
@@ -1926,7 +1926,7 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
                                               RTLIB::Libcall Call_PPCF128) {
   RTLIB::Libcall LC;
   switch (Node->getValueType(0).getSimpleVT()) {
-  default: LLVM_UNREACHABLE("Unexpected request for libcall!");
+  default: llvm_unreachable("Unexpected request for libcall!");
   case MVT::f32: LC = Call_F32; break;
   case MVT::f64: LC = Call_F64; break;
   case MVT::f80: LC = Call_F80; break;
@@ -1942,7 +1942,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
                                                RTLIB::Libcall Call_I128) {
   RTLIB::Libcall LC;
   switch (Node->getValueType(0).getSimpleVT()) {
-  default: LLVM_UNREACHABLE("Unexpected request for libcall!");
+  default: llvm_unreachable("Unexpected request for libcall!");
   case MVT::i16: LC = Call_I16; break;
   case MVT::i32: LC = Call_I32; break;
   case MVT::i64: LC = Call_I64; break;
@@ -2028,7 +2028,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   // offset depending on the data type.
   uint64_t FF;
   switch (Op0.getValueType().getSimpleVT()) {
-  default: LLVM_UNREACHABLE("Unsupported integer type!");
+  default: llvm_unreachable("Unsupported integer type!");
   case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
   case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
   case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
@@ -2147,7 +2147,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
   MVT SHVT = TLI.getShiftAmountTy();
   SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
   switch (VT.getSimpleVT()) {
-  default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!");
+  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
   case MVT::i16:
     Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@@ -2192,7 +2192,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
                                              DebugLoc dl) {
   switch (Opc) {
-  default: LLVM_UNREACHABLE("Cannot expand this yet!");
+  default: llvm_unreachable("Cannot expand this yet!");
   case ISD::CTPOP: {
     static const uint64_t mask[6] = {
       0x5555555555555555ULL, 0x3333333333333333ULL,
@@ -2306,7 +2306,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
     else if (VT.isFloatingPoint())
       Results.push_back(DAG.getConstantFP(0, VT));
     else
-      LLVM_UNREACHABLE("Unknown value type!");
+      llvm_unreachable("Unknown value type!");
     break;
   }
   case ISD::TRAP: {
@@ -2810,7 +2810,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
       // type in some cases cases.
       // Also, we can fall back to a division in some cases, but that's a big
       // performance hit in the general case.
-      LLVM_UNREACHABLE("Don't know how to expand this operation yet!");
+      llvm_unreachable("Don't know how to expand this operation yet!");
     }
     if (isSigned) {
       Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
@@ -3102,7 +3102,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
         break;
     }
     if (NewInTy.isInteger())
-      LLVM_UNREACHABLE("Cannot promote Legal Integer SETCC yet");
+      llvm_unreachable("Cannot promote Legal Integer SETCC yet");
     else {
       Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
       Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 9428525cf8..1bf5b0b370 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -53,7 +53,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
     cerr << "SoftenFloatResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to soften the result of this operator!");
+    llvm_unreachable("Do not know how to soften the result of this operator!");
 
     case ISD::BIT_CONVERT: R = SoftenFloatRes_BIT_CONVERT(N); break;
     case ISD::BUILD_PAIR:  R = SoftenFloatRes_BUILD_PAIR(N); break;
@@ -541,7 +541,7 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
     cerr << "SoftenFloatOperand Op #" << OpNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to soften this operator's operand!");
+    llvm_unreachable("Do not know how to soften this operator's operand!");
 
   case ISD::BIT_CONVERT: Res = SoftenFloatOp_BIT_CONVERT(N); break;
   case ISD::BR_CC:       Res = SoftenFloatOp_BR_CC(N); break;
@@ -781,7 +781,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
     cerr << "ExpandFloatResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
+    llvm_unreachable("Do not know how to expand the result of this operator!");
 
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
@@ -1180,7 +1180,7 @@ bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
       cerr << "ExpandFloatOperand Op #" << OpNo << ": ";
       N->dump(&DAG); cerr << "\n";
   #endif
-      LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
+      llvm_unreachable("Do not know how to expand this operator's operand!");
 
     case ISD::BIT_CONVERT:     Res = ExpandOp_BIT_CONVERT(N); break;
     case ISD::BUILD_VECTOR:    Res = ExpandOp_BUILD_VECTOR(N); break;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 63ddbed18d..600185be97 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -45,7 +45,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
     cerr << "PromoteIntegerResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to promote this operator!");
+    llvm_unreachable("Do not know how to promote this operator!");
   case ISD::AssertSext:  Res = PromoteIntRes_AssertSext(N); break;
   case ISD::AssertZext:  Res = PromoteIntRes_AssertZext(N); break;
   case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
@@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
   SDValue Res;
 
   switch (getTypeAction(N->getOperand(0).getValueType())) {
-  default: LLVM_UNREACHABLE("Unknown type action!");
+  default: llvm_unreachable("Unknown type action!");
   case Legal:
   case ExpandInteger:
     Res = N->getOperand(0);
@@ -610,7 +610,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
     cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
     N->dump(&DAG); cerr << "\n";
   #endif
-    LLVM_UNREACHABLE("Do not know how to promote this operator's operand!");
+    llvm_unreachable("Do not know how to promote this operator's operand!");
 
   case ISD::ANY_EXTEND:   Res = PromoteIntOp_ANY_EXTEND(N); break;
   case ISD::BIT_CONVERT:  Res = PromoteIntOp_BIT_CONVERT(N); break;
@@ -666,7 +666,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
   // insert sign extends for ALL conditions, but zero extend is cheaper on
   // many machines (an AND instead of two shifts), so prefer it.
   switch (CCCode) {
-  default: LLVM_UNREACHABLE("Unknown integer comparison!");
+  default: llvm_unreachable("Unknown integer comparison!");
   case ISD::SETEQ:
   case ISD::SETNE:
   case ISD::SETUGE:
@@ -923,7 +923,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
     cerr << "ExpandIntegerResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
+    llvm_unreachable("Do not know how to expand the result of this operator!");
 
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
   case ISD::SELECT:       SplitRes_SELECT(N, Lo, Hi); break;
@@ -1104,7 +1104,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
                       DAG.getConstant(~HighBitMask, ShTy));
 
     switch (N->getOpcode()) {
-    default: LLVM_UNREACHABLE("Unknown shift");
+    default: llvm_unreachable("Unknown shift");
     case ISD::SHL:
       Lo = DAG.getConstant(0, NVT);              // Low part is zero.
       Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
@@ -1132,7 +1132,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
                                  Amt);
     unsigned Op1, Op2;
     switch (N->getOpcode()) {
-    default: LLVM_UNREACHABLE("Unknown shift");
+    default: llvm_unreachable("Unknown shift");
     case ISD::SHL:  Op1 = ISD::SHL; Op2 = ISD::SRL; break;
     case ISD::SRL:
     case ISD::SRA:  Op1 = ISD::SRL; Op2 = ISD::SHL; break;
@@ -1172,7 +1172,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
 
   SDValue Lo1, Hi1, Lo2, Hi2;
   switch (N->getOpcode()) {
-  default: LLVM_UNREACHABLE("Unknown shift");
+  default: llvm_unreachable("Unknown shift");
   case ISD::SHL:
     // ShAmt < NVTBits
     Lo1 = DAG.getConstant(0, NVT);                  // Low part is zero.
@@ -1792,7 +1792,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
   }
 
   if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
-    LLVM_UNREACHABLE("Unsupported shift!");
+    llvm_unreachable("Unsupported shift!");
 }
 
 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
@@ -1968,7 +1968,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
     cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
     N->dump(&DAG); cerr << "\n";
   #endif
-    LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
+    llvm_unreachable("Do not know how to expand this operator's operand!");
 
   case ISD::BIT_CONVERT:       Res = ExpandOp_BIT_CONVERT(N); break;
   case ISD::BR_CC:             Res = ExpandIntOp_BR_CC(N); break;
@@ -2050,7 +2050,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
   // FIXME: This generated code sucks.
   ISD::CondCode LowCC;
   switch (CCCode) {
-  default: LLVM_UNREACHABLE("Unknown integer setcc!");
+  default: llvm_unreachable("Unknown integer setcc!");
   case ISD::SETLT:
   case ISD::SETULT: LowCC = ISD::SETULT; break;
   case ISD::SETGT:
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index f8d198a34b..1f05e8dc6c 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -150,7 +150,7 @@ void DAGTypeLegalizer::PerformExpensiveChecks() {
         if (Mapped & 128)
           cerr << " WidenedVectors";
         cerr << "\n";
-        llvm_unreachable();
+        llvm_unreachable(0);
       }
     }
   }
@@ -432,7 +432,7 @@ NodeDone:
 
     if (Failed) {
       I->dump(&DAG); cerr << "\n";
-      llvm_unreachable();
+      llvm_unreachable(0);
     }
   }
 #endif
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 013b18b8ef..fe2660963d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -41,7 +41,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
     cerr << "ScalarizeVectorResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!");
+    llvm_unreachable("Do not know how to scalarize the result of this operator!");
 
   case ISD::BIT_CONVERT:       R = ScalarizeVecRes_BIT_CONVERT(N); break;
   case ISD::BUILD_VECTOR:      R = N->getOperand(0); break;
@@ -278,7 +278,7 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
       cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
       N->dump(&DAG); cerr << "\n";
 #endif
-      LLVM_UNREACHABLE("Do not know how to scalarize this operator's operand!");
+      llvm_unreachable("Do not know how to scalarize this operator's operand!");
     case ISD::BIT_CONVERT:
       Res = ScalarizeVecOp_BIT_CONVERT(N);
       break;
@@ -378,7 +378,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
     cerr << "SplitVectorResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to split the result of this operator!");
+    llvm_unreachable("Do not know how to split the result of this operator!");
 
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
   case ISD::SELECT:       SplitRes_SELECT(N, Lo, Hi); break;
@@ -576,7 +576,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
   SDValue VLo, VHi;
   MVT InVT = N->getOperand(0).getValueType();
   switch (getTypeAction(InVT)) {
-  default: LLVM_UNREACHABLE("Unexpected type action!");
+  default: llvm_unreachable("Unexpected type action!");
   case Legal: {
     MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
                                  LoVT.getVectorNumElements());
@@ -768,7 +768,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
   // Split the input.
   MVT InVT = N->getOperand(0).getValueType();
   switch (getTypeAction(InVT)) {
-  default: LLVM_UNREACHABLE("Unexpected type action!");
+  default: llvm_unreachable("Unexpected type action!");
   case Legal: {
     MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
                                  LoVT.getVectorNumElements());
@@ -928,7 +928,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
       cerr << "SplitVectorOperand Op #" << OpNo << ": ";
       N->dump(&DAG); cerr << "\n";
 #endif
-      LLVM_UNREACHABLE("Do not know how to split this operator's operand!");
+      llvm_unreachable("Do not know how to split this operator's operand!");
 
     case ISD::BIT_CONVERT:       Res = SplitVecOp_BIT_CONVERT(N); break;
     case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@@ -1117,7 +1117,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
     cerr << "WidenVectorResult #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to widen the result of this operator!");
+    llvm_unreachable("Do not know how to widen the result of this operator!");
 
   case ISD::BIT_CONVERT:       Res = WidenVecRes_BIT_CONVERT(N); break;
   case ISD::BUILD_VECTOR:      Res = WidenVecRes_BUILD_VECTOR(N); break;
@@ -1773,7 +1773,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
     cerr << "WidenVectorOperand op #" << ResNo << ": ";
     N->dump(&DAG); cerr << "\n";
 #endif
-    LLVM_UNREACHABLE("Do not know how to widen this operator's operand!");
+    llvm_unreachable("Do not know how to widen this operator's operand!");
 
   case ISD::BIT_CONVERT:        Res = WidenVecOp_BIT_CONVERT(N); break;
   case ISD::CONCAT_VECTORS:     Res = WidenVecOp_CONCAT_VECTORS(N); break;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 52626db269..515ec91af9 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -140,7 +140,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
     cerr << "*** Scheduling failed! ***\n";
     PredSU->dump(this);
     cerr << " has been released too many times!\n";
-    llvm_unreachable();
+    llvm_unreachable(0);
   }
 #endif
   
@@ -569,7 +569,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
       }
 
       if (!CurSU) {
-        LLVM_UNREACHABLE("Unable to resolve live physical register dependencies!");
+        llvm_unreachable("Unable to resolve live physical register dependencies!");
       }
     }
 
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index afce34879c..c91ab660dc 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -114,7 +114,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
     cerr << "*** Scheduling failed! ***\n";
     SuccSU->dump(this);
     cerr << " has been released too many times!\n";
-    llvm_unreachable();
+    llvm_unreachable(0);
   }
 #endif
   
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 85794b95ad..7c309901a4 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -203,7 +203,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
     cerr << "*** Scheduling failed! ***\n";
     PredSU->dump(this);
     cerr << " has been released too many times!\n";
-    llvm_unreachable();
+    llvm_unreachable(0);
   }
 #endif
   
@@ -830,7 +830,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
     cerr << "*** Scheduling failed! ***\n";
     SuccSU->dump(this);
     cerr << " has been released too many times!\n";
-    llvm_unreachable();
+    llvm_unreachable(0);
   }
 #endif
   
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 80a8ae92c7..0cc8bbad57 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -431,7 +431,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
     MI->addOperand(MachineOperand::CreateImm(SubIdx));
     BB->insert(InsertPos, MI);
   } else
-    LLVM_UNREACHABLE("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
+    llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
      
   SDValue Op(Node, 0);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
@@ -552,10 +552,10 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
 #ifndef NDEBUG
     Node->dump(DAG);
 #endif
-    LLVM_UNREACHABLE("This target-independent node should have been selected!");
+    llvm_unreachable("This target-independent node should have been selected!");
     break;
   case ISD::EntryToken:
-    LLVM_UNREACHABLE("EntryToken should have been excluded from the schedule!");
+    llvm_unreachable("EntryToken should have been excluded from the schedule!");
     break;
   case ISD::TokenFactor: // fall thru
     break;
@@ -619,7 +619,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
       ++i;  // Skip the ID value.
         
       switch (Flags & 7) {
-      default: LLVM_UNREACHABLE("Bad flags!");
+      default: llvm_unreachable("Bad flags!");
       case 2:   // Def of register.
         for (; NumVals; --NumVals, ++i) {
           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 98841f876d..caa3ce1857 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -54,7 +54,7 @@ static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
 
 static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
   switch (VT.getSimpleVT()) {
-  default: LLVM_UNREACHABLE("Unknown FP format");
+  default: llvm_unreachable("Unknown FP format");
   case MVT::f32:     return &APFloat::IEEEsingle;
   case MVT::f64:     return &APFloat::IEEEdouble;
   case MVT::f80:     return &APFloat::x87DoubleExtended;
@@ -244,7 +244,7 @@ ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
 /// if the operation does not depend on the sign of the input (setne and seteq).
 static int isSignedOp(ISD::CondCode Opcode) {
   switch (Opcode) {
-  default: LLVM_UNREACHABLE("Illegal integer setcc operation!");
+  default: llvm_unreachable("Illegal integer setcc operation!");
   case ISD::SETEQ:
   case ISD::SETNE: return 0;
   case ISD::SETLT:
@@ -364,7 +364,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
   switch (N->getOpcode()) {
   case ISD::TargetExternalSymbol:
   case ISD::ExternalSymbol:
-    LLVM_UNREACHABLE("Should only be used on nodes with operands");
+    llvm_unreachable("Should only be used on nodes with operands");
   default: break;  // Normal nodes don't need extra info.
   case ISD::ARG_FLAGS:
     ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits());
@@ -627,7 +627,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
   bool Erased = false;
   switch (N->getOpcode()) {
   case ISD::EntryToken:
-    LLVM_UNREACHABLE("EntryToken should not be in CSEMaps!");
+    llvm_unreachable("EntryToken should not be in CSEMaps!");
     return false;
   case ISD::HANDLENODE: return false;  // noop.
   case ISD::CONDCODE:
@@ -669,7 +669,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
       !N->isMachineOpcode() && !doNotCSE(N)) {
     N->dump(this);
     cerr << "\n";
-    LLVM_UNREACHABLE("Node is not in map!");
+    llvm_unreachable("Node is not in map!");
   }
 #endif
   return Erased;
@@ -1443,7 +1443,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
       const APInt &C1 = N1C->getAPIntValue();
 
       switch (Cond) {
-      default: LLVM_UNREACHABLE("Unknown integer setcc!");
+      default: llvm_unreachable("Unknown integer setcc!");
       case ISD::SETEQ:  return getConstant(C1 == C2, VT);
       case ISD::SETNE:  return getConstant(C1 != C2, VT);
       case ISD::SETULT: return getConstant(C1.ult(C2), VT);
@@ -2372,7 +2372,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
   case ISD::MERGE_VALUES:
   case ISD::CONCAT_VECTORS:
     return Operand;         // Factor, merge or concat of one node?  No need.
-  case ISD::FP_ROUND: LLVM_UNREACHABLE("Invalid method to make FP_ROUND node");
+  case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
   case ISD::FP_EXTEND:
     assert(VT.isFloatingPoint() &&
            Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
@@ -2947,7 +2947,7 @@ SDValue SelectionDAG::getNode(un