Add bswap, rotl, and rotr nodes

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 65 insertions, 2 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 30a4c9f637..1d356689fb 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1133,8 +1133,6 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
                                                  N1),
                        DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
   }
-  
-  
   // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
   if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
     ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
@@ -1180,6 +1178,42 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
     WorkList.push_back(ORNode.Val);
     return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
   }
+  // canonicalize shl to left side in a shl/srl pair, to match rotate
+  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
+    std::swap(N0, N1);
+  // check for rotl, rotr
+  if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
+      N0.getOperand(0) == N1.getOperand(0) &&
+      TLI.isOperationLegal(ISD::ROTL, VT)) {
+    // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
+    if (N0.getOperand(1).getOpcode() == ISD::Constant &&
+        N1.getOperand(1).getOpcode() == ISD::Constant) {
+      uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
+      uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
+      if ((c1val + c2val) == OpSizeInBits)
+        return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+    }
+    // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
+    if (N1.getOperand(1).getOpcode() == ISD::SUB &&
+        N0.getOperand(1) == N1.getOperand(1).getOperand(1))
+      if (ConstantSDNode *SUBC = 
+          dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
+        if (SUBC->getValue() == OpSizeInBits)
+          return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+    // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
+    if (N0.getOperand(1).getOpcode() == ISD::SUB &&
+        N1.getOperand(1) == N0.getOperand(1).getOperand(1))
+      if (ConstantSDNode *SUBC = 
+          dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
+        if (SUBC->getValue() == OpSizeInBits) {
+          if (TLI.isOperationLegal(ISD::ROTR, VT))
+            return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 
+                               N1.getOperand(1));
+          else
+            return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
+                               N0.getOperand(1));
+        }
+  }
   return SDOperand();
 }
 
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index db5c8e2ff9..fe6c476817 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2112,6 +2112,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     }
     break;
 
+  case ISD::ROTL:
+  case ISD::ROTR:
+    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
+    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
+    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+    case TargetLowering::Custom:
+    case TargetLowering::Promote:
+    case TargetLowering::Expand:
+      assert(0 && "Cannot handle this yet!");
+    case TargetLowering::Legal:
+      if (Tmp1 != Node->getOperand(0) ||
+          Tmp2 != Node->getOperand(1))
+        Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
+                             Tmp2);
+      break;
+    }
+    break;
+    
   case ISD::CTPOP:
   case ISD::CTTZ:
   case ISD::CTLZ:
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5a0e2bf386..4ecea2f42b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -983,6 +983,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
+  case ISD::ROTL:
+  case ISD::ROTR:
     assert(VT == N1.getValueType() &&
            "Shift operators return type must be the same as their first arg");
     assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) &&
@@ -1039,6 +1041,12 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
       case ISD::SHL  : return getConstant(C1 << C2, VT);
       case ISD::SRL  : return getConstant(C1 >> C2, VT);
       case ISD::SRA  : return getConstant(N1C->getSignExtended() >>(int)C2, VT);
+      case ISD::ROTL : 
+        return getConstant((C1 << C2) | (C1 >> (MVT::getSizeInBits(VT) - C2)),
+                           VT);
+      case ISD::ROTR : 
+        return getConstant((C1 >> C2) | (C1 << (MVT::getSizeInBits(VT) - C2)), 
+                           VT);
       default: break;
       }
     } else {      // Cannonicalize constant to RHS if commutative
@@ -1915,6 +1923,9 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::SHL:    return "shl";
   case ISD::SRA:    return "sra";
   case ISD::SRL:    return "srl";
+  case ISD::ROTL:   return "rotl";
+  case ISD::ROTR:   return "rotr";
+  case ISD::BSWAP:  return "bswap";
   case ISD::FADD:   return "fadd";
   case ISD::FSUB:   return "fsub";
   case ISD::FMUL:   return "fmul";