diff options
author | Stuart Hastings <stuart@apple.com> | 2011-06-06 16:44:31 +0000 |
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committer | Stuart Hastings <stuart@apple.com> | 2011-06-06 16:44:31 +0000 |
commit | 57f1fde7fcda84a7e1d7490163fbad18c3755d40 (patch) | |
tree | d7cbfa7db5a6fa810808b111372e7f0c4e7757e0 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
parent | 7c48913af62ced0da03ba58755cf5f53ad587ba8 (diff) |
Avoid FGETSIGN of 80-bit types. Fixes PR10085.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132681 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 403d0d9fb2..cf6069a2f1 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1760,18 +1760,20 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, break; } case ISD::BITCAST: - // If this is an FP->Int bitcast and if the sign bit is the only thing that - // is demanded, turn this into a FGETSIGN. + // If this is an FP->Int bitcast and if the sign bit is the only + // thing demanded, turn this into a FGETSIGN. if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { - EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? - Op.getValueType() : MVT::i32; + bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); + bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); + if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { + EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); - if (Ty != Op.getValueType()) + unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); + if (!OpVTLegal && OpVTSizeInBits > 32) Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); |