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| author | Devang Patel <dpatel@apple.com> | 2011-01-26 18:42:32 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2011-01-26 18:42:32 +0000 |
| commit | 6f121fdede373a84f20785d7d30077667528dcdc (patch) | |
| tree | 5ac216317f8badfc78e94cdf3fb6818eefb6f9b2 /lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | |
| parent | 55d20e8ff1e458f177302386d14f1a4dbdd86028 (diff) | |
Process valid SDDbgValues even if the node does not have any order assigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124301 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 4c9158a452..2d7178b143 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -539,8 +539,12 @@ static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, SmallSet<unsigned, 8> &Seen) { unsigned Order = DAG->GetOrdering(N); - if (!Order || !Seen.insert(Order)) + if (!Order || !Seen.insert(Order)) { + // Process any valid SDDbgValues even if node does not have any order + // assigned. + ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); return; + } MachineBasicBlock *BB = Emitter.getBlock(); if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) { |