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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-01-12 19:06:44 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-01-12 19:06:44 +0000 |
| commit | 4dc478308f0de13d9ce20915193ac8c3318c5bd6 (patch) | |
| tree | 9d13732c71847fea363a48ddd2852feb64875da8 /lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | edaf85606d7ac8368dd7fa0e9fd4042e523a6e3a (diff) | |
When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 2dade85832..3989295ff5 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -508,9 +508,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { EVT VT = Op.getValueType(); - // Make sure that the SRA and SRL instructions are available. + // Make sure that the SRA and SHL instructions are available. if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || - TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) + TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) return DAG.UnrollVectorOp(Op.getNode()); DebugLoc DL = Op.getDebugLoc(); @@ -521,7 +521,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT); Op = Op.getOperand(0); - Op = DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz); + Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); } |