Merge information about the number of zero, one, and sign bits of live-out registers

at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 7 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 98582ba99f..8adaf057c0 100644
--- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -127,10 +127,13 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
       // Mark values used outside their block as exported, by allocating
       // a virtual register for them.
-      if (isUsedOutsideOfDefiningBlock(I))
+      if (!EnableFastISel && isa<PHINode>(I)) {
+        PHIDestRegs.insert(InitializeRegForValue(I));
+      } else if (isUsedOutsideOfDefiningBlock(I)) {
         if (!isa<AllocaInst>(I) ||
             !StaticAllocaMap.count(cast<AllocaInst>(I)))
           InitializeRegForValue(I);
+      }
 
       // Collect llvm.dbg.declare information. This is done now instead of
       // during the initial isel pass through the IR so that it is done
@@ -219,6 +222,9 @@ void FunctionLoweringInfo::clear() {
   CatchInfoFound.clear();
 #endif
   LiveOutRegInfo.clear();
+  VisitedBBs.clear();
+  PHIDestRegs.clear();
+  PHISrcToDestMap.clear();
   ArgDbgValues.clear();
   ByValArgFrameIndexMap.clear();
   RegFixups.clear();