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authorDuncan Sands <baldrick@free.fr>2009-10-14 16:11:37 +0000
committerDuncan Sands <baldrick@free.fr>2009-10-14 16:11:37 +0000
commitb01bbdcc1af27bd90b552bb1b62b48916e0d4be3 (patch)
tree724ab8850796ff140c0c5381ceb40929197922a4 /lib/CodeGen/SelectionDAG/FastISel.cpp
parent8db2cd1fc767086f65b5f93d9c7b4c1924774775 (diff)
I don't see any point in having both eh.selector.i32 and eh.selector.i64,
so get rid of eh.selector.i64 and rename eh.selector.i32 to eh.selector. Likewise for eh.typeid.for. This aligns us with gcc, which always uses a 32 bit value for the selector on all platforms. My understanding is that the register allocator used to assert if the selector intrinsic size didn't match the pointer size, and this was the reason for introducing the two variants. However my testing shows that this is no longer the case (I fixed some bugs in selector lowering yesterday, and some more today in the fastisel path; these might have caused the original problems). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84106 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/FastISel.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp25
1 files changed, 17 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index ee408dcb26..8e955aff98 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -442,15 +442,11 @@ bool FastISel::SelectCall(User *I) {
}
break;
}
- case Intrinsic::eh_selector_i32:
- case Intrinsic::eh_selector_i64: {
+ case Intrinsic::eh_selector: {
EVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
default: break;
case TargetLowering::Expand: {
- EVT VT = (IID == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
-
if (MMI) {
if (MBB->isLandingPad())
AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
@@ -464,12 +460,25 @@ bool FastISel::SelectCall(User *I) {
}
unsigned Reg = TLI.getExceptionSelectorRegister();
- const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
+ EVT SrcVT = TLI.getPointerTy();
+ const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
unsigned ResultReg = createResultReg(RC);
- bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- Reg, RC, RC);
+ bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
+ RC, RC);
assert(InsertedCopy && "Can't copy address registers!");
InsertedCopy = InsertedCopy;
+
+ // Cast the register to the type of the selector.
+ if (SrcVT.bitsGT(MVT::i32))
+ ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
+ ResultReg);
+ else if (SrcVT.bitsLT(MVT::i32))
+ ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
+ ISD::SIGN_EXTEND, ResultReg);
+ if (ResultReg == 0)
+ // Unhandled operand. Halt "fast" selection and bail.
+ return false;
+
UpdateValueMap(I, ResultReg);
} else {
unsigned ResultReg =