diff options
| author | Chris Lattner <sabre@nondot.org> | 2004-06-02 05:57:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-06-02 05:57:12 +0000 |
| commit | 9bcdcd17c7219dbc68de2f11ca2de86471c8c390 (patch) | |
| tree | 60173becc7cd0c79edcc9869fd6d82d0b4cd5f86 /lib/CodeGen/RegAllocSimple.cpp | |
| parent | 62d6ad2cee0e6b7fa653c8903a951f8497b6da3a (diff) | |
Adjust to new TargetMachine interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13956 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 1b7f5471b4..4e825b233e 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // a preliminary pass that will invalidate any registers that // are used by the instruction (including implicit uses) unsigned Opcode = MI->getOpcode(); - const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); + const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode); const unsigned *Regs = Desc.ImplicitUses; while (*Regs) RegsUsed[*Regs++] = true; @@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { if (op.isDef()) { - if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) { + if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) { physReg = getFreeReg(virtualReg); } else { // must be same register number as the first operand |