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authorBill Wendling <isanbard@gmail.com>2006-11-28 22:48:48 +0000
committerBill Wendling <isanbard@gmail.com>2006-11-28 22:48:48 +0000
commita09362eb975730ac624c0bd210a95655ee105296 (patch)
tree7c1bf798b031cbf652aa3adca54677ce8a2df20d /lib/CodeGen/RegAllocSimple.cpp
parent3e3bcbf3a056a2f3a681326c491e84a089a063ab (diff)
Use llvm streams instead of <iostream>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31985 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp11
1 files changed, 5 insertions, 6 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 088be47e14..f08b039b82 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -190,9 +190,9 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
- DEBUG(std::cerr << "op: " << op << "\n");
- DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, TM));
+ DOUT << "op: " << op << "\n";
+ DOUT << "\t inst[" << i << "]: ";
+ DEBUG(MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
@@ -221,8 +221,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
}
MI->getOperand(i).setReg(physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getReg() << "\n");
+ DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
}
}
RegClassIdx.clear();
@@ -234,7 +233,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
/// runOnMachineFunction - Register allocate the whole function
///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
- DEBUG(std::cerr << "Machine Function " << "\n");
+ DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();