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| author | Devang Patel <dpatel@apple.com> | 2008-12-23 21:55:04 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2008-12-23 21:55:04 +0000 |
| commit | 2755896fd048d189bedc5e99e776b3eca010dd4e (patch) | |
| tree | ceb7fe42ae61701422b3349e15abb9c4fcca166a /lib/CodeGen/RegAllocSimple.cpp | |
| parent | 0b1d4a798d1dd2f39521b6b381cd1c1911c9ab52 (diff) | |
Silience unused warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61390 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 7dc98904ab..5e5290ce3e 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -122,7 +122,9 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif while (1) { unsigned regIdx = RegClassIdx[RC]++; |