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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-14 04:30:51 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-14 04:30:51 +0000
commit7ff82e1501c416552125f77a62edebe576e469b0 (patch)
treed0b741af7760c88cff28ff7fe2b7ce8a0f127b4a /lib/CodeGen/RegAllocFast.cpp
parent22c687b6421d9cc03351ddb0c7fd3d45382bc01a (diff)
Enable opportunistic coalescing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103764 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocFast.cpp')
-rw-r--r--lib/CodeGen/RegAllocFast.cpp25
1 files changed, 18 insertions, 7 deletions
diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp
index 66ba86ac94..e1066bf1e7 100644
--- a/lib/CodeGen/RegAllocFast.cpp
+++ b/lib/CodeGen/RegAllocFast.cpp
@@ -603,6 +603,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
reservePhysReg(MBB, MII, *I);
SmallVector<unsigned, 8> VirtKills, PhysKills, PhysDefs;
+ SmallVector<MachineInstr*, 32> Coalesced;
// Otherwise, sequentially allocate each instruction in the MBB.
while (MII != MBB.end()) {
@@ -706,8 +707,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
if (MO.isUse()) {
unsigned PhysReg = reloadVirtReg(MBB, MI, i, Reg, CopyDst);
- if (CopySrc == Reg)
- CopySrc = PhysReg;
+ CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
setPhysReg(MO, PhysReg);
if (MO.isKill())
VirtKills.push_back(Reg);
@@ -757,11 +757,12 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
PhysKills.push_back(Reg);
continue;
}
- if (MO.isDead())
- VirtKills.push_back(Reg);
unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, CopySrc);
- if (CopyDst == Reg)
- CopyDst = PhysReg;
+ if (MO.isDead()) {
+ VirtKills.push_back(Reg);
+ CopyDst = 0; // cancel coalescing;
+ } else
+ CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
setPhysReg(MO, PhysReg);
}
@@ -783,7 +784,12 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
MRI->addPhysRegsUsed(UsedInInstr);
- DEBUG(dbgs() << "<< " << *MI);
+ if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
+ DEBUG(dbgs() << "-- coalescing: " << *MI);
+ Coalesced.push_back(MI);
+ } else {
+ DEBUG(dbgs() << "<< " << *MI);
+ }
}
// Spill all physical registers holding virtual registers now.
@@ -795,6 +801,11 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
spillVirtReg(MBB, MI, i, true);
LiveVirtRegs.clear();
+ // Erase all the coalesced copies. We are delaying it until now because
+ // LiveVirtsRegs might refer to the instrs.
+ for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
+ MBB.erase(Coalesced[i]);
+
DEBUG(MBB.dump());
}