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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-06 23:26:25 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-06 23:26:25 +0000
commited2185e171a86b8c0e166803fd4066383a6cff08 (patch)
treeebf3d2c29b2dc9f75970cbf95665c42540c4e7bd /lib/CodeGen/ProcessImplicitDefs.cpp
parentfca3a25fed9950f7ca39c86a3f2b72a1966f7896 (diff)
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
INSERT_SUBREG will now only appear in SSA machine instructions. Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant since partial redef COPY instructions appear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107726 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ProcessImplicitDefs.cpp')
-rw-r--r--lib/CodeGen/ProcessImplicitDefs.cpp22
1 files changed, 21 insertions, 1 deletions
diff --git a/lib/CodeGen/ProcessImplicitDefs.cpp b/lib/CodeGen/ProcessImplicitDefs.cpp
index 0195918a11..80121ca0f2 100644
--- a/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -117,10 +117,24 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
}
}
+ // Eliminate %reg1032:sub<def> = COPY undef.
+ if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
+ MachineOperand &MO = MI->getOperand(1);
+ if (ImpDefRegs.count(MO.getReg())) {
+ if (MO.isKill()) {
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
+ vi.removeKill(MI);
+ }
+ MI->eraseFromParent();
+ Changed = true;
+ continue;
+ }
+ }
+
bool ChangedToImpDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse() || MO.isUndef())
+ if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
continue;
unsigned Reg = MO.getReg();
if (!Reg)
@@ -145,6 +159,12 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
Changed = true;
MO.setIsUndef();
+ // This is a partial register redef of an implicit def.
+ // Make sure the whole register is defined by the instruction.
+ if (MO.isDef()) {
+ MI->addRegisterDefined(Reg);
+ continue;
+ }
if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
// Make sure other uses of
for (unsigned j = i+1; j != e; ++j) {