Merge commit 'a662a9862501fc86904e90054f7c1519101d9126'

Conflicts:
	include/llvm/CodeGen/IntrinsicLowering.h
	include/llvm/MC/MCAssembler.h
	include/llvm/MC/MCObjectStreamer.h
	lib/LLVMBuild.txt
	lib/Linker/LinkArchives.cpp
	lib/MC/MCAssembler.cpp
	lib/MC/MCELFStreamer.cpp
	lib/MC/MCParser/AsmParser.cpp
	lib/MC/MCPureStreamer.cpp
	lib/MC/WinCOFFStreamer.cpp
	lib/Makefile
	lib/Support/Unix/Memory.inc
	lib/Support/Unix/Process.inc
	lib/Support/Unix/Program.inc
	lib/Target/ARM/ARM.h
	lib/Target/ARM/ARMFastISel.cpp
	lib/Target/ARM/ARMISelLowering.cpp
	lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
	lib/Target/Mips/MipsInstrFPU.td
	lib/Target/X86/CMakeLists.txt
	lib/Target/X86/X86ISelLowering.cpp
	lib/Target/X86/X86TargetMachine.cpp
	lib/Target/X86/X86TargetObjectFile.cpp
	lib/Transforms/InstCombine/InstCombineCalls.cpp
	test/CodeGen/X86/fast-isel-x86-64.ll
	tools/llc/llc.cpp
	tools/lto/LTOModule.cpp
	utils/TableGen/EDEmitter.cpp

1 files changed, 3 insertions, 5 deletions

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 8892e846fa..488f1d4564 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -30,6 +30,7 @@
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterClassInfo.h"
@@ -464,13 +465,10 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
   MO.setIsKill(false);
   bool AllDead = true;
   const unsigned SuperReg = MO.getReg();
+  MachineInstrBuilder MIB(MF, MI);
   for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
     if (LiveRegs.test(*SubRegs)) {
-      MI->addOperand(MachineOperand::CreateReg(*SubRegs,
-                                               true  /*IsDef*/,
-                                               true  /*IsImp*/,
-                                               false /*IsKill*/,
-                                               false /*IsDead*/));
+      MIB.addReg(*SubRegs, RegState::ImplicitDefine);
       AllDead = false;
     }
   }