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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-10 01:29:16 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-10 01:29:16 +0000 |
| commit | 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 (patch) | |
| tree | ffcb01b1621bcedb427d701cfaee9ea9a19b0a2c /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 920a2089d9b737820631bc6de4c4fb9fa9ad1e07 (diff) | |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index f0bd6d1372..bd5b2b898b 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -213,7 +213,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); const TargetMachine &TM = Fn.getTarget(); - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); + const InstrItineraryData *InstrItins = TM.getInstrItineraryData(); ScheduleHazardRecognizer *HR = TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins); AntiDepBreaker *ADB = |