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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-03-10 00:36:06 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-03-10 00:36:06 +0000 |
commit | 64ffa83c9bf5a1f0c064295de9b3eba7b0f09a99 (patch) | |
tree | 68d6a05c351643690ff5b183f030a0693d007e9d /lib/CodeGen/MachineVerifier.cpp | |
parent | 1efd6b94a917449da5007fd332cd895692aa0319 (diff) |
Add SSA verification to MachineVerifier.
Somehow we never verified SSA dominance before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152458 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | lib/CodeGen/MachineVerifier.cpp | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index f26886fd20..91a536d063 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -1014,8 +1014,18 @@ void MachineVerifier::visitMachineFunctionAfter() { } // Now check liveness info if available - if (LiveVars || LiveInts) - calcRegsRequired(); + calcRegsRequired(); + + if (MRI->isSSA() && !MF->empty()) { + BBInfo &MInfo = MBBInfoMap[&MF->front()]; + for (RegSet::iterator + I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; + ++I) { + report("Virtual register def doesn't dominate all uses.", MF); + *OS << "- register:\t" << PrintReg(*I) << '\n'; + } + } + if (LiveVars) verifyLiveVariables(); if (LiveInts) |