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authorAndrew Trick <atrick@apple.com>2012-05-17 22:37:09 +0000
committerAndrew Trick <atrick@apple.com>2012-05-17 22:37:09 +0000
commit5429a6b0d5ed57bf9a924fa5d88c80c0357b7e08 (patch)
tree5172e2fb0c33475896fd7bf2633ac634fe4584f7 /lib/CodeGen/MachineScheduler.cpp
parent0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe (diff)
comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineScheduler.cpp')
-rw-r--r--lib/CodeGen/MachineScheduler.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp
index 0aaef5d599..207d65a6b9 100644
--- a/lib/CodeGen/MachineScheduler.cpp
+++ b/lib/CodeGen/MachineScheduler.cpp
@@ -1,4 +1,4 @@
-//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//excess
+//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -808,7 +808,8 @@ traceCandidate(const char *Label, unsigned QID, SUnit *SU,
}
#endif
-/// Return true if the LHS reg pressure effect is better than RHS.
+/// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
+/// more desirable than RHS from scheduling standpoint.
static bool compareRPDelta(const RegPressureDelta &LHS,
const RegPressureDelta &RHS) {
// Compare each component of pressure in decreasing order of importance