diff options
| author | Nick Lewycky <nicholas@mxc.ca> | 2011-10-13 00:54:59 +0000 |
|---|---|---|
| committer | Nick Lewycky <nicholas@mxc.ca> | 2011-10-13 00:54:59 +0000 |
| commit | 3821b1885e13dcdda6aa2853f1317d3288256685 (patch) | |
| tree | 9449152cb178ed8a2911ecba4ad6dc1a20ceb225 /lib/CodeGen/MachineInstr.cpp | |
| parent | fc61a23506fdad8f38e3437d741a4108339abcfe (diff) | |
Add missing braces to pacify GCC's -Wparentheses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 0ef1ef603b..a240667f7d 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -1473,11 +1473,12 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { } unsigned RCID = 0; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) + if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { if (TM) OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); else OS << ":RC" << RCID; + } unsigned TiedTo = 0; if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) |