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authorChris Lattner <sabre@nondot.org>2006-05-04 00:49:59 +0000
committerChris Lattner <sabre@nondot.org>2006-05-04 00:49:59 +0000
commit34fb2cad46adb39f3c2cc705fbbf439a383d0f65 (patch)
tree73c46a70e95a7f953905e62585d43fe4b5b19ebb /lib/CodeGen/MachineInstr.cpp
parent10f3597c4e0c13ecf0272b7ca0be741a91ade48c (diff)
Remove some more V9-specific stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28092 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
-rw-r--r--lib/CodeGen/MachineInstr.cpp34
1 files changed, 2 insertions, 32 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 8889a7aea2..3d65dfd31b 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -176,18 +176,6 @@ static void print(const MachineOperand &MO, std::ostream &OS,
if (TM) MRI = TM->getRegisterInfo();
- bool CloseParen = true;
- if (MO.isHiBits32())
- OS << "%lm(";
- else if (MO.isLoBits32())
- OS << "%lo(";
- else if (MO.isHiBits64())
- OS << "%hh(";
- else if (MO.isLoBits64())
- OS << "%hm(";
- else
- CloseParen = false;
-
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.getVRegValue()) {
@@ -235,9 +223,6 @@ static void print(const MachineOperand &MO, std::ostream &OS,
default:
assert(0 && "Unrecognized operand type");
}
-
- if (CloseParen)
- OS << ")";
}
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
@@ -272,8 +257,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
OS << "\n";
}
-namespace llvm {
-std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
+std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
// If the instruction is embedded into a basic block, we can find the target
// info for the instruction.
if (const MachineBasicBlock *MBB = MI.getParent()) {
@@ -301,16 +285,7 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
return os << "\n";
}
-std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
- if (MO.isHiBits32())
- OS << "%lm(";
- else if (MO.isLoBits32())
- OS << "%lo(";
- else if (MO.isHiBits64())
- OS << "%hh(";
- else if (MO.isLoBits64())
- OS << "%hm(";
-
+std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
@@ -356,10 +331,5 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
break;
}
- if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
- OS << ")";
-
return OS;
}
-
-}