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| author | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:51:21 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:51:21 +0000 |
| commit | d10a53d5a1a5f5a729b55638acfb25d3871df70b (patch) | |
| tree | 10e27235a58c5a6ece04ce523798cc1d228efa09 /lib/CodeGen/MachineInstr.cpp | |
| parent | b200f1c28ee49fcb7876406fd26debc20cecbc5f (diff) | |
fix a bunch of partially ambiguous patterns on ARM. As an
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97955 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions