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| author | Jim Grosbach <grosbach@apple.com> | 2012-03-30 18:53:01 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-30 18:53:01 +0000 |
| commit | a45e3747e612c00ca4933087d883db77f4547571 (patch) | |
| tree | ae355131579aa49623670813430f6bfe8d45dfa7 /lib/CodeGen/MachineFunction.cpp | |
| parent | 8f1148bd07d57a1324ed39250642119baa540b7c (diff) | |
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions