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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-14 23:53:23 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-14 23:53:23 +0000 |
| commit | d5d61edfc66887b3b1962251da877b284b1478ab (patch) | |
| tree | 3aca64dc6753489a18e43c53178cb4a3f1babd46 /lib/CodeGen/InterferenceCache.cpp | |
| parent | cac5fa39bd861861018bb2c3f0b36cc71c2caa38 (diff) | |
Fix global live range splitting regmask accuracy.
Pretend that regmask interference ends at the 'dead' slot, even when
there is other interference ending at the 'reg' slot of the same
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150531 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/InterferenceCache.cpp')
| -rw-r--r-- | lib/CodeGen/InterferenceCache.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/InterferenceCache.cpp b/lib/CodeGen/InterferenceCache.cpp index a8a32f3f1a..9eb8a75843 100644 --- a/lib/CodeGen/InterferenceCache.cpp +++ b/lib/CodeGen/InterferenceCache.cpp @@ -185,7 +185,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) { // Also check for register mask interference. SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start; - for (unsigned i = RegMaskSlots.size(); i && RegMaskSlots[i-1] > Limit; --i) + for (unsigned i = RegMaskSlots.size(); + i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) { // Register mask i-1 clobbers PhysReg after the LIU interference. // Model the regmask clobber as a dead def. |