diff options
author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-02-23 13:39:13 +0000 |
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committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-02-23 13:39:13 +0000 |
commit | 92fc97afa742000aeb81d862abbaaba50b27a000 (patch) | |
tree | e4375fce8b88f0146e6d2024afec993f0fa57952 /lib/CodeGen/DFAPacketizer.cpp | |
parent | 1b14f20ef7b35b9209ba6ab394773278936babe9 (diff) |
Strip a layer of boilerplate from the VLIWPacketizer by storing the scheduler as an opaque pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151252 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/DFAPacketizer.cpp')
-rw-r--r-- | lib/CodeGen/DFAPacketizer.cpp | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp index 5c8feb1466..f0cf290825 100644 --- a/lib/CodeGen/DFAPacketizer.cpp +++ b/lib/CodeGen/DFAPacketizer.cpp @@ -104,8 +104,8 @@ namespace { // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides // Schedule method to build the dependence graph. // -// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so cannot be exposed to the -// VLIWPacketizerImpl interface, even as an undefined pointer. +// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so we have to reference it as +// an opaque pointer in VLIWPacketizerList. class DefaultVLIWScheduler : public ScheduleDAGInstrs { public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, @@ -113,18 +113,7 @@ public: // Schedule - Actual scheduling work. void Schedule(); }; -} - -namespace llvm { -// Wrapper for holding library-local data types. -class VLIWPacketizerImpl { -public: - DefaultVLIWScheduler DAGBuilder; - VLIWPacketizerImpl(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT, bool IsPostRA) - : DAGBuilder(MF, MLI, MDT, IsPostRA) {} -}; -} +} // end anonymous namespace DefaultVLIWScheduler::DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, @@ -143,12 +132,12 @@ VLIWPacketizerList::VLIWPacketizerList( bool IsPostRA) : TM(MF.getTarget()), MF(MF) { TII = TM.getInstrInfo(); ResourceTracker = TII->CreateTargetScheduleState(&TM, 0); - Impl = new VLIWPacketizerImpl(MF, MLI, MDT, IsPostRA); + SchedulerImpl = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA); } // VLIWPacketizerList Dtor VLIWPacketizerList::~VLIWPacketizerList() { - delete Impl; + delete (DefaultVLIWScheduler *)SchedulerImpl; delete ResourceTracker; } @@ -195,10 +184,11 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr) { - Impl->DAGBuilder.Run(MBB, BeginItr, EndItr, MBB->size()); + DefaultVLIWScheduler *Scheduler = (DefaultVLIWScheduler *)SchedulerImpl; + Scheduler->Run(MBB, BeginItr, EndItr, MBB->size()); // Remember scheduling units. - SUnits = Impl->DAGBuilder.SUnits; + SUnits = Scheduler->SUnits; // Generate MI -> SU map. std::map <MachineInstr*, SUnit*> MIToSUnit; |