PNaCl wire format: Remove the top-level DATALAYOUT record

PNaCl only supports a fixed data layout, so treat this as implicit in
the pexe file.

Add the data layout field back at read time, to prevent accidentally
using any architecture-specific backend data layout when translating,
and to ensure that any IR passes that use the data layout work
correctly.

BUG=https://code.google.com/p/nativeclient/issues/detail?id=3505
TEST=*.ll tests + PNaCl toolchain trybots

Review URL: https://codereview.chromium.org/17591014

1 files changed, 0 insertions, 3 deletions

diff --git a/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp b/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp
index bf1faa463d..7afcf666dc 100644
--- a/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp
+++ b/lib/Bitcode/NaCl/Writer/NaClBitcodeWriter.cpp
@@ -431,9 +431,6 @@ static void WriteModuleInfo(const Module *M, const NaClValueEnumerator &VE,
                             NaClBitstreamWriter &Stream) {
   DEBUG(dbgs() << "-> WriteModuleInfo\n");
   // Emit various pieces of data attached to a module.
-  if (!M->getDataLayout().empty())
-    WriteStringRecord(naclbitc::MODULE_CODE_DATALAYOUT, M->getDataLayout(),
-                      0/*TODO*/, Stream);
   if (!M->getModuleInlineAsm().empty())
     WriteStringRecord(naclbitc::MODULE_CODE_ASM, M->getModuleInlineAsm(),
                       0/*TODO*/, Stream);