Add documentation comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155203 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 0 deletions

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 6a321ea2cf..e3f4c6465d 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -402,6 +402,11 @@ class Instruction {
 
   string AsmMatchConverter = "";
 
+  /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
+  /// two-operand matcher inst-alias for a three operand instruction.
+  /// For example, the arm instruction "add r3, r3, r5" can be written
+  /// as "add r3, r5". The constraint is of the same form as a tied-operand
+  /// constraint. For example, "$Rn = $Rd".
   string TwoOperandAliasConstraint = "";
 
   ///@}