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authorDan Gohman <gohman@apple.com>2009-04-03 00:25:26 +0000
committerDan Gohman <gohman@apple.com>2009-04-03 00:25:26 +0000
commit8f9643f0f768d5dcff0ffea1de6191dba1b5b083 (patch)
treef246f1e82d6bb08c3b214a627b51e517c44c2d22 /include/llvm
parent25f0ee5191f8460099cfa9897f7a1750b79bfa98 (diff)
Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG and TargetInstrInfo::EXTRACT_SUBREG, which are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h12
-rw-r--r--include/llvm/Target/TargetSelectionDAG.td5
2 files changed, 0 insertions, 17 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 6cea5d6d7a..7d748259cf 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -327,18 +327,6 @@ namespace ISD {
/// elements 1 to N-1 of the N-element vector are undefined.
SCALAR_TO_VECTOR,
- // EXTRACT_SUBREG - This node is used to extract a sub-register value.
- // This node takes a superreg and a constant sub-register index as operands.
- // Note sub-register indices must be increasing. That is, if the
- // sub-register index of a 8-bit sub-register is N, then the index for a
- // 16-bit sub-register must be at least N+1.
- EXTRACT_SUBREG,
-
- // INSERT_SUBREG - This node is used to insert a sub-register value.
- // This node takes a superreg, a subreg value, and a constant sub-register
- // index as operands.
- INSERT_SUBREG,
-
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*N], then return the top part.
MULHU, MULHS,
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 5d1b37d1c7..7f39bb2f83 100644
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -406,11 +406,6 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
-def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
- SDTypeProfile<1, 2, []>>;
-def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
- SDTypeProfile<1, 3, []>>;
-
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.
def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",