Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21409 91177308-0d34-0410-b5e6-96231b3b80d8

20 files changed, 191 insertions, 191 deletions

diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index 512cae7927..f28c00faee 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -1,10 +1,10 @@
 //===-- llvm/CodeGen/AsmPrinter.h - AsmPrinter Framework --------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This class is intended to be used as a base class for target-specific
@@ -78,7 +78,7 @@ namespace llvm {
     /// AsciiDirective - This directive allows emission of an ascii string with
     /// the standard C escape characters embedded into it.
     const char *AsciiDirective;
-    
+
     /// DataDirectives - These directives are used to output some unit of
     /// integer data to the current section.  If a data directive is set to
     /// null, smaller data directives will be used to emit the large sizes.
diff --git a/include/llvm/CodeGen/InstrScheduling.h b/include/llvm/CodeGen/InstrScheduling.h
index 816aa7e806..c9aee2244a 100644
--- a/include/llvm/CodeGen/InstrScheduling.h
+++ b/include/llvm/CodeGen/InstrScheduling.h
@@ -1,10 +1,10 @@
 //===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a minimal, but complete, interface to instruction
@@ -22,7 +22,7 @@ class TargetMachine;
 
 //---------------------------------------------------------------------------
 // Function: createScheduleInstructionsWithSSAPass(..)
-// 
+//
 // Purpose:
 //   Entry point for instruction scheduling on SSA form.
 //   Schedules the machine instructions generated by instruction selection.
diff --git a/include/llvm/CodeGen/IntrinsicLowering.h b/include/llvm/CodeGen/IntrinsicLowering.h
index b15d505308..12b9624860 100644
--- a/include/llvm/CodeGen/IntrinsicLowering.h
+++ b/include/llvm/CodeGen/IntrinsicLowering.h
@@ -1,12 +1,12 @@
 //===-- IntrinsicLowering.h - Intrinsic Function Lowering -------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file defines the IntrinsicLowering interface.  This interface allows
 // addition of domain-specific or front-end specific intrinsics to LLVM without
 // having to modify all of the code generators to support the new intrinsic.
@@ -38,7 +38,7 @@
 namespace llvm {
   class CallInst;
   class Module;
-  
+
   class IntrinsicLowering {
   public:
     virtual ~IntrinsicLowering() {}
@@ -67,7 +67,7 @@ namespace llvm {
   /// implementation to allow for future extensibility.
   struct DefaultIntrinsicLowering : public IntrinsicLowering {
     virtual void AddPrototypes(Module &M);
-    virtual void LowerIntrinsicCall(CallInst *CI);    
+    virtual void LowerIntrinsicCall(CallInst *CI);
   };
 }
 
diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h
index 17c1e2a770..5cb9b98661 100644
--- a/include/llvm/CodeGen/LiveVariables.h
+++ b/include/llvm/CodeGen/LiveVariables.h
@@ -1,12 +1,12 @@
 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file implements the LiveVariable analysis pass.  For each machine
 // instruction in the function, this pass calculates the set of registers that
 // are immediately dead after the instruction (i.e., the instruction calculates
@@ -23,7 +23,7 @@
 // to resolve physical register lifetimes in each basic block).  If a physical
 // register is not register allocatable, it is not tracked.  This is useful for
 // things like the stack pointer and condition codes.
-//   
+//
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
@@ -111,7 +111,7 @@ public:
   /// killed_iterator - Iterate over registers killed by a machine instruction
   ///
   typedef std::multimap<MachineInstr*, unsigned>::iterator killed_iterator;
-  
+
   /// killed_begin/end - Get access to the range of registers killed by a
   /// machine instruction.
   killed_iterator killed_begin(MachineInstr *MI) {
diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h
index 3f781222c9..b354f71f4e 100644
--- a/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/include/llvm/CodeGen/MachineBasicBlock.h
@@ -1,12 +1,12 @@
 //===-- llvm/CodeGen/MachineBasicBlock.h ------------------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // Collect the sequence of machine instructions for a basic block.
 //
 //===----------------------------------------------------------------------===//
@@ -75,7 +75,7 @@ public:
   }
 
   ~MachineBasicBlock();
-  
+
   /// getBasicBlock - Return the LLVM basic block that this instance
   /// corresponded to originally.
   ///
@@ -111,7 +111,7 @@ public:
   typedef std::vector<MachineBasicBlock *>::const_iterator const_pred_iterator;
   typedef std::vector<MachineBasicBlock *>::iterator       succ_iterator;
   typedef std::vector<MachineBasicBlock *>::const_iterator const_succ_iterator;
-  
+
   pred_iterator        pred_begin()       { return Predecessors.begin (); }
   const_pred_iterator  pred_begin() const { return Predecessors.begin (); }
   pred_iterator        pred_end()         { return Predecessors.end ();   }
@@ -162,7 +162,7 @@ public:
   iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }
   MachineInstr *remove(MachineInstr *I)  { return Insts.remove(I); }
   void clear()                           { Insts.clear(); }
-  
+
   /// splice - Take a block of instructions from MBB 'Other' in the range [From,
   /// To), and insert them into this MBB right before 'where'.
   void splice(iterator where, MachineBasicBlock *Other, iterator From,
@@ -219,10 +219,10 @@ template <> struct GraphTraits<MachineBasicBlock *> {
   typedef MachineBasicBlock::succ_iterator ChildIteratorType;
 
   static NodeType *getEntryNode(MachineBasicBlock *BB) { return BB; }
-  static inline ChildIteratorType child_begin(NodeType *N) { 
+  static inline ChildIteratorType child_begin(NodeType *N) {
     return N->succ_begin();
   }
-  static inline ChildIteratorType child_end(NodeType *N) { 
+  static inline ChildIteratorType child_end(NodeType *N) {
     return N->succ_end();
   }
 };
@@ -232,10 +232,10 @@ template <> struct GraphTraits<const MachineBasicBlock *> {
   typedef MachineBasicBlock::const_succ_iterator ChildIteratorType;
 
   static NodeType *getEntryNode(const MachineBasicBlock *BB) { return BB; }
-  static inline ChildIteratorType child_begin(NodeType *N) { 
+  static inline ChildIteratorType child_begin(NodeType *N) {
     return N->succ_begin();
   }
-  static inline ChildIteratorType child_end(NodeType *N) { 
+  static inline ChildIteratorType child_end(NodeType *N) {
     return N->succ_end();
   }
 };
@@ -252,10 +252,10 @@ template <> struct GraphTraits<Inverse<MachineBasicBlock*> > {
   static NodeType *getEntryNode(Inverse<MachineBasicBlock *> G) {
     return G.Graph;
   }
-  static inline ChildIteratorType child_begin(NodeType *N) { 
+  static inline ChildIteratorType child_begin(NodeType *N) {
     return N->pred_begin();
   }
-  static inline ChildIteratorType child_end(NodeType *N) { 
+  static inline ChildIteratorType child_end(NodeType *N) {
     return N->pred_end();
   }
 };
@@ -264,12 +264,12 @@ template <> struct GraphTraits<Inverse<const MachineBasicBlock*> > {
   typedef const MachineBasicBlock NodeType;
   typedef MachineBasicBlock::const_pred_iterator ChildIteratorType;
   static NodeType *getEntryNode(Inverse<const MachineBasicBlock*> G) {
-    return G.Graph; 
+    return G.Graph;
   }
-  static inline ChildIteratorType child_begin(NodeType *N) { 
+  static inline ChildIteratorType child_begin(NodeType *N) {
     return N->pred_begin();
   }
-  static inline ChildIteratorType child_end(NodeType *N) { 
+  static inline ChildIteratorType child_end(NodeType *N) {
     return N->pred_end();
   }
 };
diff --git a/include/llvm/CodeGen/MachineCodeEmitter.h b/include/llvm/CodeGen/MachineCodeEmitter.h
index 562d4c695e..f3155ba7f7 100644
--- a/include/llvm/CodeGen/MachineCodeEmitter.h
+++ b/include/llvm/CodeGen/MachineCodeEmitter.h
@@ -1,10 +1,10 @@
 //===-- llvm/CodeGen/MachineCodeEmitter.h - Code emission -------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines an abstract interface that is used by the machine code
@@ -37,7 +37,7 @@ public:
   /// about to be code generated.
   ///
   virtual void startFunction(MachineFunction &F) {}
-  
+
   /// finishFunction - This callback is invoked when the specified function has
   /// finished code generation.
   ///
@@ -88,7 +88,7 @@ public:
   /// addRelocation - Whenever a relocatable address is needed, it should be
   /// noted with this interface.
   virtual void addRelocation(const MachineRelocation &MR) = 0;
-  
+
   // getConstantPoolEntryAddress - Return the address of the 'Index' entry in
   // the constant pool that was last emitted with the 'emitConstantPool' method.
   //
diff --git a/include/llvm/CodeGen/MachineConstantPool.h b/include/llvm/CodeGen/MachineConstantPool.h
index edfd601faa..0e6c642e8e 100644
--- a/include/llvm/CodeGen/MachineConstantPool.h
+++ b/include/llvm/CodeGen/MachineConstantPool.h
@@ -1,12 +1,12 @@
 //===-- CodeGen/MachineConstantPool.h - Abstract Constant Pool --*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // The MachineConstantPool class keeps track of constants referenced by a
 // function which must be spilled to memory.  This is used for constants which
 // are unable to be used directly as operands to instructions, which typically
diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h
index 7ac582c75d..8f8a852480 100644
--- a/include/llvm/CodeGen/MachineFrameInfo.h
+++ b/include/llvm/CodeGen/MachineFrameInfo.h
@@ -1,12 +1,12 @@
 //===-- CodeGen/MachineFrameInfo.h - Abstract Stack Frame Rep. --*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // The MachineFrameInfo class represents an abstract stack frame until
 // prolog/epilog code is inserted.  This class is key to allowing stack frame
 // representation optimizations, such as frame pointer elimination.  It also
@@ -168,7 +168,7 @@ public:
   ///
   bool hasCalls() const { return HasCalls; }
   void setHasCalls(bool V) { HasCalls = V; }
-  
+
   /// getMaxCallFrameSize - Return the maximum size of a call frame that must be
   /// allocated for an outgoing function call.  This is only available if
   /// CallFrameSetup/Destroy pseudo instructions are used by the target, and
@@ -186,7 +186,7 @@ public:
     Objects.insert(Objects.begin(), StackObject(Size, 1, SPOffset));
     return -++NumFixedObjects;
   }
-  
+
   /// CreateStackObject - Create a new statically sized stack object, returning
   /// a postive identifier to represent it.
   ///
diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h
index 1121fd0480..bc4c4c4f92 100644
--- a/include/llvm/CodeGen/MachineFunction.h
+++ b/include/llvm/CodeGen/MachineFunction.h
@@ -1,18 +1,18 @@
 //===-- llvm/CodeGen/MachineFunction.h --------------------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // Collect native machine code for a function.  This class contains a list of
 // MachineBasicBlock instances that make up the current compiled function.
 //
 // This class also contains pointers to various classes which hold
 // target-specific information about the generated code.
-//   
+//
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
@@ -35,19 +35,19 @@ struct ilist_traits<MachineBasicBlock> {
   // this is only set by the MachineFunction owning the ilist
   friend class MachineFunction;
   MachineFunction* Parent;
-  
+
 public:
   ilist_traits<MachineBasicBlock>() : Parent(0) { }
-  
+
   static MachineBasicBlock* getPrev(MachineBasicBlock* N) { return N->Prev; }
   static MachineBasicBlock* getNext(MachineBasicBlock* N) { return N->Next; }
-  
+
   static const MachineBasicBlock*
   getPrev(const MachineBasicBlock* N) { return N->Prev; }
-  
+
   static const MachineBasicBlock*
   getNext(const MachineBasicBlock* N) { return N->Next; }
-  
+
   static void setPrev(MachineBasicBlock* N, MachineBasicBlock* prev) {
     N->Prev = prev;
   }
@@ -179,7 +179,7 @@ public:
   /// is an error to add the same register to the same set more than once.
   void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
   void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
-  
+
   // Iteration support for live in/out sets.  These sets are kept in sorted
   // order by their register number.
   typedef std::vector<unsigned>::const_iterator liveinout_iterator;
@@ -219,7 +219,7 @@ public:
   /// in your path.
   ///
   void viewCFG() const;
-  
+
   /// viewCFGOnly - This function is meant for use from the debugger.  It works
   /// just like viewCFG, but it does not include the contents of basic blocks
   /// into the nodes, just the label.  If you are only interested in the CFG
@@ -256,7 +256,7 @@ public:
   // Provide accessors for basic blocks...
   const BasicBlockListType &getBasicBlockList() const { return BasicBlocks; }
         BasicBlockListType &getBasicBlockList()       { return BasicBlocks; }
- 
+
   //===--------------------------------------------------------------------===//
   // BasicBlock iterator forwarding functions
   //
@@ -331,7 +331,7 @@ template <> struct GraphTraits<const MachineFunction*> :
 };
 
 
-// Provide specializations of GraphTraits to be able to treat a function as a 
+// Provide specializations of GraphTraits to be able to treat a function as a
 // graph of basic blocks... and to walk it in inverse order.  Inverse order for
 // a function is considered to be when traversing the predecessor edges of a BB
 // instead of the successor edges.
diff --git a/include/llvm/CodeGen/MachineFunctionPass.h b/include/llvm/CodeGen/MachineFunctionPass.h
index 390dcb8562..973babd702 100644
--- a/include/llvm/CodeGen/MachineFunctionPass.h
+++ b/include/llvm/CodeGen/MachineFunctionPass.h
@@ -1,10 +1,10 @@
 //===-- MachineFunctionPass.h - Pass for MachineFunctions --------*-C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the MachineFunctionPass class.  MachineFunctionPass's are
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 6a6d380fef..ea2233f8d2 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -1,10 +1,10 @@
 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declaration of the MachineInstr class, which is the
@@ -35,8 +35,8 @@ template <typename T> struct ilist;
 typedef short MachineOpCode;
 
 //===----------------------------------------------------------------------===//
-// class MachineOperand 
-// 
+// class MachineOperand
+//
 // Purpose:
 //   Representation of each machine instruction operand.
 //   This class is designed so that you can allocate a vector of operands
@@ -45,10 +45,10 @@ typedef short MachineOpCode;
 //   E.g, for this VM instruction:
 //		ptr = alloca type, numElements
 //   we generate 2 machine instructions on the SPARC:
-// 
+//
 //		mul Constant, Numelements -> Reg
 //		add %sp, Reg -> Ptr
-// 
+//
 //   Each instruction has 3 operands, listed above.  Of those:
 //   -	Reg, NumElements, and Ptr are of operand type MO_Register.
 //   -	Constant is of operand type MO_SignExtendedImmed on the SPARC.
@@ -57,16 +57,16 @@ typedef short MachineOpCode;
 //	
 //   -  Reg will be of virtual register type MO_MInstrVirtualReg.  The field
 //	MachineInstr* minstr will point to the instruction that computes reg.
-// 
+//
 //   -	%sp will be of virtual register type MO_MachineReg.
 //	The field regNum identifies the machine register.
-// 
+//
 //   -	NumElements will be of virtual register type MO_VirtualReg.
 //	The field Value* value identifies the value.
-// 
+//
 //   -	Ptr will also be of virtual register type MO_VirtualReg.
 //	Again, the field Value* value identifies the value.
-// 
+//
 //===----------------------------------------------------------------------===//
 
 struct MachineOperand {
@@ -108,14 +108,14 @@ public:
     MO_ExternalSymbol,          // Name of external global symbol
     MO_GlobalAddress,           // Address of a global value
   };
-  
+
 private:
   union {
     Value*  value;      // BasicBlockVal for a label operand.
                         // ConstantVal for a non-address immediate.
                         // Virtual register for an SSA operand,
                         //   including hidden operands required for
-                        //   the generated machine code.     
+                        //   the generated machine code.
                         // LLVM global for MO_GlobalAddress.
 
     int64_t immedVal;		// Constant value for an explicit constant
@@ -134,7 +134,7 @@ private:
                                 // valid for MO_GlobalAddress and MO_ExternalSym
   } extra;
 
-  void zeroContents () { 
+  void zeroContents () {
     memset (&contents, 0, sizeof (contents));
     memset (&extra, 0, sizeof (extra));
   }
@@ -193,9 +193,9 @@ public:
     extra = M.extra;
   }
 
- 
+
   ~MachineOperand() {}
-  
+
   const MachineOperand &operator=(const MachineOperand &MO) {
     contents = MO.contents;
     flags    = MO.flags;
@@ -205,7 +205,7 @@ public:
   }
 
   /// getType - Returns the MachineOperandType for this operand.
-  /// 
+  ///
   MachineOperandType getType() const { return opType; }
 
   /// getUseType - Returns the MachineOperandUseType of this operand.
@@ -245,7 +245,7 @@ public:
   /// has one. This is deprecated and only used by the SPARC v9 backend.
   ///
   Value* getVRegValueOrNull() const {
-    return (opType == MO_VirtualRegister || opType == MO_CCRegister || 
+    return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
             isPCRelativeDisp()) ? contents.value : NULL;
   }
 
@@ -312,7 +312,7 @@ public:
   ///
   bool hasAllocatedReg() const {
     return (extra.regNum >= 0 &&
-            (opType == MO_VirtualRegister || opType == MO_CCRegister || 
+            (opType == MO_VirtualRegister || opType == MO_CCRegister ||
              opType == MO_MachineRegister));
   }
 
@@ -331,13 +331,13 @@ public:
     // code.' It's not clear where the duplication is.
     assert(hasAllocatedReg() && "This operand cannot have a register number!");
     extra.regNum = Reg;
-  }  
+  }
 
   void setValueReg(Value *val) {
     assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*");
     contents.value = val;
   }
-  
+
   void setImmedValue(int immVal) {
     assert(isImmediate() && "Wrong MachineOperand mutator");
     contents.immedVal = immVal;
@@ -358,35 +358,35 @@ public:
   void markLo32()      { flags |= LOFLAG32; }
   void markHi64()      { flags |= HIFLAG64; }
   void markLo64()      { flags |= LOFLAG64; }
-  
+
 private:
   /// setRegForValue - Replaces the Value with its corresponding physical
   /// register after register allocation is complete. This is deprecated
   /// and only used by the SPARC v9 back-end.
   ///
   void setRegForValue(int reg) {
-    assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 
+    assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
 	   opType == MO_MachineRegister);
     extra.regNum = reg;
   }
-  
+
   friend class MachineInstr;
 };
 
 
 //===----------------------------------------------------------------------===//
-// class MachineInstr 
-// 
+// class MachineInstr
+//
 // Purpose:
 //   Representation of each machine instruction.
-// 
+//
 //   MachineOpCode must be an enum, defined separately for each target.
 //   E.g., It is defined in SparcInstructionSelection.h for the SPARC.
-// 
+//
 //  There are 2 kinds of operands:
-// 
-//  (1) Explicit operands of the machine instruction in vector operands[] 
-// 
+//
+//  (1) Explicit operands of the machine instruction in vector operands[]
+//
 //  (2) "Implicit operands" are values implicitly used or defined by the
 //      machine instruction, such as arguments to a CALL, return value of
 //      a CALL (if any), and return value of a RETURN.
@@ -426,7 +426,7 @@ public:
   /// block.
   ///
   MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
-  
+
   ~MachineInstr();
 
   const MachineBasicBlock* getParent() const { return parent; }
@@ -439,7 +439,7 @@ public:
   /// Access to explicit operands of the instruction.
   ///
   unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
-  
+
   const MachineOperand& getOperand(unsigned i) const {
     assert(i < getNumOperands() && "getOperand() out of range!");
     return operands[i];
@@ -454,7 +454,7 @@ public:
   // This returns the i'th entry in the operand vector.
   // That represents the i'th explicit operand or the (i-N)'th implicit operand,
   // depending on whether i < N or i >= N.
-  // 
+  //
   const MachineOperand& getExplOrImplOperand(unsigned i) const {
     assert(i < operands.size() && "getExplOrImplOperand() out of range!");
     return (i < getNumOperands()? getOperand(i)
@@ -463,9 +463,9 @@ public:
 
   //
   // Access to implicit operands of the instruction
-  // 
+  //
   unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
-  
+
   MachineOperand& getImplicitOp(unsigned i) {
     assert(i < numImplicitRefs && "implicit ref# out of range!");
     return operands[i + operands.size() - numImplicitRefs];
@@ -672,7 +672,7 @@ public:
   /// replace - Support to rewrite a machine instruction in place: for now,
   /// simply replace() and then set new operands with Set.*Operand methods
   /// below.
-  /// 
+  ///
   void replace(short Opcode, unsigned numOperands);
 
   /// setOpcode - Replace the opcode of the current instruction with a new one.
@@ -687,7 +687,7 @@ public:
   }
 
   // Access to set the operands when building the machine instruction
-  // 
+  //
   void SetMachineOperandVal(unsigned i,
                             MachineOperand::MachineOperandType operandType,
                             Value* V);
@@ -702,22 +702,22 @@ public:
   unsigned substituteValue(const Value* oldVal, Value* newVal,
                            bool defsOnly, bool notDefsAndUses,
                            bool& someArgsWereIgnored);
-  
+
   // SetRegForOperand -
   // SetRegForImplicitRef -
   // Mark an explicit or implicit operand with its allocated physical register.
-  // 
+  //
   void SetRegForOperand(unsigned i, int regNum);
   void SetRegForImplicitRef(unsigned i, int regNum);
 
   //
   // Iterator to enumerate machine operands.
-  // 
+  //
   template<class MITy, class VTy>
   class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
     unsigned i;
     MITy MI;
-    
+
     void skipToNextVal() {
       while (i < MI->getNumOperands() &&
              !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
@@ -725,14 +725,14 @@ public:
                 && MI->getOperand(i).getVRegValue() != 0))
         ++i;
     }
-  
+
     inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
       skipToNextVal();
     }
-  
+
   public:
     typedef ValOpIterator<MITy, VTy> _Self;
-    
+
     inline VTy operator*() const {
       return MI->getOperand(i).getVRegValue();
     }
@@ -742,16 +742,16 @@ public:
 
     inline VTy operator->() const { return operator*(); }
 
-    inline bool isUse()   const { return MI->getOperand(i).isUse(); } 
-    inline bool isDef()   const { return MI->getOperand(i).isDef(); } 
+    inline bool isUse()   const { return MI->getOperand(i).isUse(); }
+    inline bool isDef()   const { return MI->getOperand(i).isDef(); }
 
     inline _Self& operator++() { i++; skipToNextVal(); return *this; }
     inline _Self  operator++(int) { _Self tmp = *this; ++*this; return tmp; }
 
-    inline bool operator==(const _Self &y) const { 
+    inline bool operator==(const _Self &y) const {
       return i == y.i;
     }
-    inline bool operator!=(const _Self &y) const { 
+    inline bool operator!=(const _Self &y) const {
       return !operator==(y);
     }
 
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 060f90c53f..2aee02ee6c 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -1,10 +1,10 @@
 //===-- CodeGen/MachineInstBuilder.h - Simplify creation of MIs -*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file exposes a function named BuildMI, which is useful for dramatically
@@ -86,7 +86,7 @@ public:
     MI->addMachineRegOperand(Reg, Ty);
     return *this;
   }
-  
+
   /// addImm - Add a new immediate operand.
   ///
   const MachineInstrBuilder &addImm(int Val) const {
diff --git a/include/llvm/CodeGen/MachineRelocation.h b/include/llvm/CodeGen/MachineRelocation.h
index a72f29dd0f..93d2527ab6 100644
--- a/include/llvm/CodeGen/MachineRelocation.h
+++ b/include/llvm/CodeGen/MachineRelocation.h
@@ -1,10 +1,10 @@
 //===-- llvm/CodeGen/MachineRelocation.h - Target Relocation ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines the MachineRelocation class.
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 866d07ff43..a053dd95a6 100644
--- a/