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| author | Nate Begeman <natebegeman@mac.com> | 2008-05-12 19:40:03 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2008-05-12 19:40:03 +0000 |
| commit | b43e9c196542acc80c9e4643809661065710848f (patch) | |
| tree | c9a051f8d4f23bd728271be046655591057750de /include/llvm/CodeGen/SelectionDAGNodes.h | |
| parent | e4fc1ccd4dd66a7421e911528c1af5337c20167b (diff) | |
Add support for vicmp/vfcmp codegen, more legalize support coming.
This is necessary to unbreak the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/SelectionDAGNodes.h')
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index f2ff91abf3..5cfc1661a0 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -332,6 +332,14 @@ namespace ISD { // (op #2) as a CondCodeSDNode. SETCC, + // Vector SetCC operator - This evaluates to a vector of integer elements + // with the high bit in each element set to true if the comparison is true + // and false if the comparison is false. All other bits in each element + // are undefined. The operands to this are the left and right operands + // to compare (ops #0, and #1) and the condition code to compare them with + // (op #2) as a CondCodeSDNode. + VSETCC, + // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded // integer shift operations, just like ADD/SUB_PARTS. The operation // ordering is: |