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| author | Bill Wendling <isanbard@gmail.com> | 2010-01-23 10:26:57 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-01-23 10:26:57 +0000 |
| commit | 187361b056823df4ff292561fe47468dad956872 (patch) | |
| tree | 892d1e4b759b29ec8caea499a41df85b38eafb81 /include/llvm/CodeGen/SchedulerRegistry.h | |
| parent | e88a8e6fbf4ea8163eebdbc2f72fa08d72a02532 (diff) | |
Remove the '-disable-scheduling' flag and replace it with the 'source' option of
the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/SchedulerRegistry.h')
| -rw-r--r-- | include/llvm/CodeGen/SchedulerRegistry.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index 1cf64a09a7..cf3274f4a9 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -73,6 +73,11 @@ ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel); +/// createBURRListDAGScheduler - This creates a bottom up register usage +/// reduction list scheduler that schedules in source code order when possible. +ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, + CodeGenOpt::Level OptLevel); + /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, |