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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-18 20:50:30 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-01-18 20:50:30 +0000 |
| commit | a402271351ba498a5d2bcae99a502c78a6fb15e1 (patch) | |
| tree | 971be7017ea7c1afc56ef73a13491cd20c8e95c3 /include/llvm/CodeGen/ISDOpcodes.h | |
| parent | bfab85e9b187f8e59c7638c15347319799097ae1 (diff) | |
Document the fact that the selection dag changes the vselect condition type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148411 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/ISDOpcodes.h')
| -rw-r--r-- | include/llvm/CodeGen/ISDOpcodes.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index cb990edac1..8fb76040e8 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -323,6 +323,9 @@ namespace ISD { // and #2), returning a vector result. All vectors have the same length. // Much like the scalar select and setcc, each bit in the condition selects // whether the corresponding result element is taken from op #1 or op #2. + // At first, the VSELECT condition is of vXi1 type. Later, targets may change + // the condition type in order to match the VSELECT node using a a pattern. + // The condition follows the BooleanContent format of the target. VSELECT, // Select with condition operator - This selects between a true value and |