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| author | Jan Voung <jvoung@chromium.org> | 2013-05-22 14:34:10 -0700 |
|---|---|---|
| committer | Jan Voung <jvoung@chromium.org> | 2013-05-22 14:34:10 -0700 |
| commit | 501900058c0815d35e630d416e3d4e1373b75b9c (patch) | |
| tree | 4d75fbe1728d3922cce31a3c29247e89dd5e0c50 /include/llvm/Bitcode/NaCl/NaClBitCodes.h | |
| parent | 9f0ec130483d6bfb0357dcf05b49fa91d6c265f5 (diff) | |
Promote bswap i16, i32, and i64 to be allowed llvm intrinsics.
Disallow i1, i8, which don't make sense for "byte" swapping.
None of these generate outcalls to compiler_rt.
Test coverage:
* test/CodeGen/AArch64/dp1.ll (only testing i32, i64)
* test/CodeGen/ARM/rev.ll (only testing i16)
* test/CodeGen/Mips/bswap.ll (only testing i32, i64)
* test/CodeGen/X86/bswap.ll (i16, i32, i64, on i686)
* test/NaCl/{ARM,X86}/intrinsics-bitmanip.ll (i16, i32, i64)
(maybe the last set of tests could be merged into the
upstream tests)
For targets without native i16 bswap, the i16 could just be
a bswap on an i32 plus a shift right 16.
Other test coverage:
* gcc/testsuite/gcc.dg/builtin-bswap-[1,2,3,4,5].c
Misc: style cleanups, and add comments to the undocumented intrinsics in the dev list.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3378
R=dschuff@chromium.org
Review URL: https://codereview.chromium.org/14914011
Diffstat (limited to 'include/llvm/Bitcode/NaCl/NaClBitCodes.h')
0 files changed, 0 insertions, 0 deletions