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authorJF Bastien <jfb@chromium.org>2013-07-30 16:38:26 -0700
committerJF Bastien <jfb@chromium.org>2013-07-30 16:38:26 -0700
commitf75fd0a9f95109b9cb13a74aad6dcc98c3d5d625 (patch)
tree652c465d76008ef58f5c8d55827050a6f1d875e1 /docs
parent423b3bb89c78e96c59843aa7c6e55d01bde174d1 (diff)
Rewrite ``asm("":::"memory")`` to ``fence seq_cst``
This is often used as a compiler barrier and should "just work" in user code. BUG= https://code.google.com/p/nativeclient/issues/detail?id=2345 R=eliben@chromium.org TEST= (cd ./pnacl/build/llvm_x86_64 && ninja check-all) Review URL: https://codereview.chromium.org/21178002
Diffstat (limited to 'docs')
-rw-r--r--docs/PNaClDeveloperGuide.rst7
1 files changed, 7 insertions, 0 deletions
diff --git a/docs/PNaClDeveloperGuide.rst b/docs/PNaClDeveloperGuide.rst
index 7bd45dd6fd..b0a47423e3 100644
--- a/docs/PNaClDeveloperGuide.rst
+++ b/docs/PNaClDeveloperGuide.rst
@@ -130,3 +130,10 @@ As in C11/C++11:
these primitives must always be of the same bit size for that location.
- Not all memory orderings are valid for all atomic operations.
+Inline Assembly
+===============
+
+Inline assembly isn't supported by PNaCl because it isn't portable. The
+one current exception is the common compiler barrier idiom
+``asm("":::"memory")``, which gets transformed to a sequentially
+consistent memory barrier (equivalent to ``__sync_synchronize()``).