diff options
| author | Derek Schuff <dschuff@chromium.org> | 2013-01-09 16:55:43 -0800 |
|---|---|---|
| committer | Derek Schuff <dschuff@chromium.org> | 2013-01-11 13:47:37 -0800 |
| commit | b770d0e0636a4b5ad61b1ca661caee67576c05fc (patch) | |
| tree | c486ce032d41f97313c50629bd5b879f53e6ccbf /bindings/python/llvm/tests/test_disassembler.py | |
| parent | b835840cf112a6178506d834b58aa625f59a8994 (diff) | |
| parent | 1ad9253c9d34ccbce3e7e4ea5d87c266cbf93410 (diff) | |
Merge commit '1ad9253c9d34ccbce3e7e4ea5d87c266cbf93410'
deplib features commented out due to removal upstream;
will add back as a localmod
Conflicts:
include/llvm/ADT/Triple.h
include/llvm/MC/MCAssembler.h
include/llvm/Target/TargetFrameLowering.h
lib/CodeGen/AsmPrinter/DwarfDebug.cpp
lib/CodeGen/AsmPrinter/DwarfDebug.h
lib/CodeGen/BranchFolding.cpp
lib/LLVMBuild.txt
lib/Linker/LinkArchives.cpp
lib/MC/MCAssembler.cpp
lib/MC/MCELFStreamer.cpp
lib/Makefile
lib/Target/ARM/ARMExpandPseudoInsts.cpp
lib/Target/ARM/ARMFrameLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMSubtarget.h
lib/Target/ARM/ARMTargetObjectFile.cpp
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
lib/Target/Mips/MipsInstrFPU.td
lib/Target/Mips/MipsInstrInfo.td
lib/Target/X86/X86CodeEmitter.cpp
lib/Target/X86/X86Subtarget.h
lib/VMCore/Module.cpp
test/MC/MachO/ARM/nop-armv4-padding.s
tools/Makefile
tools/llc/llc.cpp
tools/lto/LTOModule.cpp
tools/lto/lto.cpp
Diffstat (limited to 'bindings/python/llvm/tests/test_disassembler.py')
| -rw-r--r-- | bindings/python/llvm/tests/test_disassembler.py | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/bindings/python/llvm/tests/test_disassembler.py b/bindings/python/llvm/tests/test_disassembler.py index 545e8668b6..46d12f7056 100644 --- a/bindings/python/llvm/tests/test_disassembler.py +++ b/bindings/python/llvm/tests/test_disassembler.py @@ -1,6 +1,6 @@ from .base import TestBase -from ..disassembler import Disassembler +from ..disassembler import Disassembler, Option_UseMarkup class TestDisassembler(TestBase): def test_instantiate(self): @@ -26,3 +26,14 @@ class TestDisassembler(TestBase): self.assertEqual(instructions[0], (0, 3, '\tjcxz\t-127')) self.assertEqual(instructions[1], (3, 2, '\taddl\t%eax, %edi')) + + def test_set_options(self): + sequence = '\x10\x40\x2d\xe9' + triple = 'arm-linux-android' + + disassembler = Disassembler(triple) + disassembler.set_options(Option_UseMarkup) + count, s = disassembler.get_instruction(sequence) + print s + self.assertEqual(count, 4) + self.assertEqual(s, '\tpush\t{<reg:r4>, <reg:lr>}') |