diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:09:50 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-03-11 23:09:50 +0000 |
| commit | f219f3135d0ec939acd42801766c17fad41c0173 (patch) | |
| tree | 7d818ecd73b7697a2307bb0ec1af0310a3e6e178 | |
| parent | b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3 (diff) | |
Pseudo-ize VMOVDcc and VMOVScc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127506 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 13 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 10 | ||||
| -rw-r--r-- | utils/TableGen/ARMDecoderEmitter.cpp | 5 |
3 files changed, 19 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index a985152701..cb2a89d01a 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -708,6 +708,19 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, switch (Opcode) { default: return false; + case ARM::VMOVScc: + case ARM::VMOVDcc: { + unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), + MI.getOperand(1).getReg()) + .addReg(MI.getOperand(2).getReg(), + getKillRegState(MI.getOperand(2).isKill())) + .addImm(MI.getOperand(3).getImm()) // 'pred' + .addReg(MI.getOperand(4).getReg()); + + MI.eraseFromParent(); + return true; + } case ARM::MOVCCr: { BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), MI.getOperand(1).getReg()) diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index a277ef797e..b8ae270157 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -972,15 +972,13 @@ def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), // let neverHasSideEffects = 1 in { -def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, - (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), - IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", +def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p), + Size4Bytes, IIC_fpUNA64, [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, RegConstraint<"$Dn = $Dd">; -def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), - IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", +def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p), + Size4Bytes, IIC_fpUNA32, [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, RegConstraint<"$Sn = $Sd">; } // neverHasSideEffects diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index aa8db1e0ba..67e2bafa8f 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1600,9 +1600,8 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, Name == "FNEGDcc") return false; - // Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc. - if (Name == "VMOVDcc" || Name == "VMOVScc" || Name == "VNEGDcc" || - Name == "VNEGScc") + // Ditto for VNEGDcc and VNEGScc. + if (Name == "VNEGDcc" || Name == "VNEGScc") return false; // LDMIA_RET is a special case of LDM (Load Multiple) where the registers |