Split EVT into MVT and EVT, the former representing _just_ a primitive type, while

the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8

86 files changed, 5644 insertions, 5542 deletions

diff --git a/include/llvm/CodeGen/DAGISelHeader.h b/include/llvm/CodeGen/DAGISelHeader.h
index d0a24ebc78..b2acbc1745 100644
--- a/include/llvm/CodeGen/DAGISelHeader.h
+++ b/include/llvm/CodeGen/DAGISelHeader.h
@@ -35,7 +35,7 @@ static bool IsChainCompatible(SDNode *Chain, SDNode *Op) {
     return false;
   if (Chain->getNumOperands() > 0) {
     SDValue C0 = Chain->getOperand(0);
-    if (C0.getValueType() == EVT::Other)
+    if (C0.getValueType() == MVT::Other)
       return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
   }
   return true;
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index b159dd970c..b2cc94db4e 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -137,24 +137,24 @@ protected:
   /// FastEmit_r - This method is called by target-independent code
   /// to request that an instruction with the given type and opcode
   /// be emitted.
-  virtual unsigned FastEmit_(EVT::SimpleValueType VT,
-                             EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_(MVT VT,
+                             MVT RetVT,
                              ISD::NodeType Opcode);
 
   /// FastEmit_r - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// register operand be emitted.
   ///
-  virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
-                              EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_r(MVT VT,
+                              MVT RetVT,
                               ISD::NodeType Opcode, unsigned Op0);
 
   /// FastEmit_rr - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// register operands be emitted.
   ///
-  virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
-                               EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_rr(MVT VT,
+                               MVT RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, unsigned Op1);
 
@@ -162,8 +162,8 @@ protected:
   /// to request that an instruction with the given type, opcode, and
   /// register and immediate operands be emitted.
   ///
-  virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
-                               EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_ri(MVT VT,
+                               MVT RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, uint64_t Imm);
 
@@ -171,8 +171,8 @@ protected:
   /// to request that an instruction with the given type, opcode, and
   /// register and floating-point immediate operands be emitted.
   ///
-  virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
-                               EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_rf(MVT VT,
+                               MVT RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, ConstantFP *FPImm);
 
@@ -180,8 +180,8 @@ protected:
   /// to request that an instruction with the given type, opcode, and
   /// register and immediate operands be emitted.
   ///
-  virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
-                                EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_rri(MVT VT,
+                                MVT RetVT,
                                 ISD::NodeType Opcode,
                                 unsigned Op0, unsigned Op1, uint64_t Imm);
 
@@ -189,33 +189,33 @@ protected:
   /// to emit an instruction with an immediate operand using FastEmit_ri.
   /// If that fails, it materializes the immediate into a register and try
   /// FastEmit_rr instead.
-  unsigned FastEmit_ri_(EVT::SimpleValueType VT,
+  unsigned FastEmit_ri_(MVT VT,
                         ISD::NodeType Opcode,
                         unsigned Op0, uint64_t Imm,
-                        EVT::SimpleValueType ImmType);
+                        MVT ImmType);
   
   /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
   /// to emit an instruction with an immediate operand using FastEmit_rf.
   /// If that fails, it materializes the immediate into a register and try
   /// FastEmit_rr instead.
-  unsigned FastEmit_rf_(EVT::SimpleValueType VT,
+  unsigned FastEmit_rf_(MVT VT,
                         ISD::NodeType Opcode,
                         unsigned Op0, ConstantFP *FPImm,
-                        EVT::SimpleValueType ImmType);
+                        MVT ImmType);
   
   /// FastEmit_i - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// immediate operand be emitted.
-  virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
-                              EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_i(MVT VT,
+                              MVT RetVT,
                               ISD::NodeType Opcode,
                               uint64_t Imm);
 
   /// FastEmit_f - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
   /// floating-point immediate operand be emitted.
-  virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
-                              EVT::SimpleValueType RetVT,
+  virtual unsigned FastEmit_f(MVT VT,
+                              MVT RetVT,
                               ISD::NodeType Opcode,
                               ConstantFP *FPImm);
 
@@ -268,12 +268,12 @@ protected:
 
   /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
   /// from a specified index of a superregister to a specified type.
-  unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
+  unsigned FastEmitInst_extractsubreg(MVT RetVT,
                                       unsigned Op0, uint32_t Idx);
 
   /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
   /// with all but the least significant bit set to zero.
-  unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
+  unsigned FastEmitZExtFromI1(MVT VT,
                               unsigned Op);
 
   /// FastEmitBranch - Emit an unconditional branch to the given block,
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 73b8895127..47df8672f4 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -193,7 +193,7 @@ public:
   /// setRoot - Set the current root tag of the SelectionDAG.
   ///
   const SDValue &setRoot(SDValue N) {
-    assert((!N.getNode() || N.getValueType() == EVT::Other) &&
+    assert((!N.getNode() || N.getValueType() == MVT::Other) &&
            "DAG root value is not a chain!");
     return Root = N;
   }
@@ -327,7 +327,7 @@ public:
                    unsigned LabelID);
 
   SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
-    return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
+    return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
                    getRegister(Reg, N.getValueType()), N);
   }
 
@@ -336,7 +336,7 @@ public:
   // null) and that there should be a flag result.
   SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
                        SDValue Flag) {
-    SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
     return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
   }
@@ -344,13 +344,13 @@ public:
   // Similar to last getCopyToReg() except parameter Reg is a SDValue
   SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
                          SDValue Flag) {
-    SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, Reg, N, Flag };
     return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
   }
 
   SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
-    SDVTList VTs = getVTList(VT, EVT::Other);
+    SDVTList VTs = getVTList(VT, MVT::Other);
     SDValue Ops[] = { Chain, getRegister(Reg, VT) };
     return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
   }
@@ -360,7 +360,7 @@ public:
   // null) and that there should be a flag result.
   SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
                            SDValue Flag) {
-    SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
+    SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
     return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
   }
@@ -391,7 +391,7 @@ public:
   /// a flag result (to ensure it's not CSE'd).  CALLSEQ_START does not have a
   /// useful DebugLoc.
   SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
-    SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
+    SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain,  Op };
     return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
                    VTs, Ops, 2);
@@ -402,7 +402,7 @@ public:
   /// a useful DebugLoc.
   SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
                            SDValue InFlag) {
-    SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
+    SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
     SmallVector<SDValue, 4> Ops;
     Ops.push_back(Chain);
     Ops.push_back(Op1);
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 7229463d4e..f1a5e2e69e 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1245,7 +1245,7 @@ public:
   /// to which the flag operand points. Otherwise return NULL.
   SDNode *getFlaggedNode() const {
     if (getNumOperands() != 0 &&
-        getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
+      getOperand(getNumOperands()-1).getValueType().getSimpleVT() == MVT::Flag)
       return getOperand(getNumOperands()-1).getNode();
     return 0;
   }
@@ -1278,7 +1278,7 @@ public:
     return ValueList[ResNo];
   }
 
-  /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
+  /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
   ///
   unsigned getValueSizeInBits(unsigned ResNo) const {
     return getValueType(ResNo).getSizeInBits();
@@ -1505,7 +1505,7 @@ public:
   explicit HandleSDNode(SDValue X)
 #endif
     : SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
-             getSDVTList(EVT::Other)) {
+             getSDVTList(MVT::Other)) {
     InitOperands(&Op, X);
   }
   ~HandleSDNode();
@@ -1914,7 +1914,7 @@ class BasicBlockSDNode : public SDNode {
   /// harder.  Let's see if we need it first.
   explicit BasicBlockSDNode(MachineBasicBlock *mbb)
     : SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
-             getSDVTList(EVT::Other)), MBB(mbb) {
+             getSDVTList(MVT::Other)), MBB(mbb) {
   }
 public:
 
@@ -1965,7 +1965,7 @@ class SrcValueSDNode : public SDNode {
   /// Create a SrcValue for a general value.
   explicit SrcValueSDNode(const Value *v)
     : SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
-             getSDVTList(EVT::Other)), V(v) {}
+             getSDVTList(MVT::Other)), V(v) {}
 
 public:
   /// getValue - return the contained Value.
@@ -1987,7 +1987,7 @@ class MemOperandSDNode : public SDNode {
   /// Create a MachineMemOperand node
   explicit MemOperandSDNode(const MachineMemOperand &mo)
     : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
-             getSDVTList(EVT::Other)), MO(mo) {}
+             getSDVTList(MVT::Other)), MO(mo) {}
 
 public:
   /// MO - The contained MachineMemOperand.
@@ -2026,7 +2026,7 @@ class DbgStopPointSDNode : public SDNode {
   DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
                      Value *cu)
     : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
-      getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
+      getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
     InitOperands(&Chain, ch);
   }
 public:
@@ -2045,7 +2045,7 @@ class LabelSDNode : public SDNode {
   unsigned LabelID;
   friend class SelectionDAG;
 LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
-    : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
+    : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
     InitOperands(&Chain, ch);
   }
 public:
@@ -2085,7 +2085,7 @@ class CondCodeSDNode : public SDNode {
   friend class Selec