Add a llvm lit test for NaCl ARM/X86 support for bswap i16, i32, i64.

Slowly trying to promote "dev" intrinsics that are being
tested to be accepted.  Luckily, bswap is supported
without compiler_rt for ARM and x86 at least.

Test at default level and -O0. Also tested by
gcc/testsuite/gcc.dg/builtin-bswap-[1,2,3,4,5].c,
and a couple of other gcc tests.

We may want to blacklist odd argument sizes
like i8, and i1, which the x86 backend won't handle.
The i16 case is also interesting, however, it's easy
to do if you have an i32 bswap.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=3378
R=eliben@chromium.org

Review URL: https://codereview.chromium.org/14971004

2 files changed, 138 insertions, 0 deletions

diff --git a/test/NaCl/ARM/intrinsics-bitmanip.ll b/test/NaCl/ARM/intrinsics-bitmanip.ll
new file mode 100644
index 0000000000..03678d3371
--- /dev/null
+++ b/test/NaCl/ARM/intrinsics-bitmanip.ll
@@ -0,0 +1,64 @@
+; RUN: llc -mtriple=armv7-unknown-nacl -filetype=asm %s -o - | FileCheck %s
+; RUN: llc -mtriple=armv7-unknown-nacl -O0 -filetype=asm %s -o - | FileCheck %s
+
+; Test that various bit manipulation intrinsics are supported by the
+; NaCl ARM backend.
+
+declare i16 @llvm.bswap.i16(i16)
+declare i32 @llvm.bswap.i32(i32)
+declare i64 @llvm.bswap.i64(i64)
+
+; CHECK: test_bswap_16
+; CHECK: rev [[REG:r[0-9]+]], {{r[0-9]+}}
+; CHECK-NEXT: lsr {{.*}}[[REG]], {{.*}}[[REG]], #16
+define i16 @test_bswap_16(i16 %a) {
+  %b = call i16 @llvm.bswap.i16(i16 %a)
+  ret i16 %b
+}
+
+; CHECK: test_bswap_const_16
+; 0xcdab
+; CHECK: movw r0, #52651
+define i16 @test_bswap_const_16() {
+  ; 0xabcd
+  %a = call i16 @llvm.bswap.i16(i16 43981)
+  ret i16 %a
+}
+
+; CHECK: test_bswap_32
+; CHECK: rev [[REG:r[0-9]+]], {{r[0-9]+}}
+define i32 @test_bswap_32(i32 %a) {
+  %b = call i32 @llvm.bswap.i32(i32 %a)
+  ret i32 %b
+}
+
+; CHECK: test_bswap_const_32
+; 0x01ef cdab
+; CHECK: movw r0, #52651
+; CHECK: movt r0, #495
+define i32 @test_bswap_const_32() {
+  ; 0xabcdef01
+  %a = call i32 @llvm.bswap.i32(i32 2882400001)
+  ret i32 %a
+}
+
+; CHECK: test_bswap_64
+; CHECK: rev [[REG1:r[0-9]+]], {{r[0-9]+}}
+; CHECK: rev {{r[0-9]+}}, {{r[0-9]+}}
+; CHECK: mov r0, {{.*}}[[REG1]]
+define i64 @test_bswap_64(i64 %a) {
+  %b = call i64 @llvm.bswap.i64(i64 %a)
+  ret i64 %b
+}
+
+; CHECK: test_bswap_const_64
+; 0x8967 4523 01ef cdab
+; Just checking movw, since O0 and O2 have different schedules for the
+; movw/movt of r0/r1.
+; CHECK: movw r0, #52651
+; CHECK: movw r1, #17699
+define i64 @test_bswap_const_64() {
+  ; 0xabcdef01 23456789
+  %a = call i64 @llvm.bswap.i64(i64 12379813738877118345)
+  ret i64 %a
+}
diff --git a/test/NaCl/X86/intrinsics-bitmanip.ll b/test/NaCl/X86/intrinsics-bitmanip.ll
new file mode 100644
index 0000000000..bab38811b0
--- /dev/null
+++ b/test/NaCl/X86/intrinsics-bitmanip.ll
@@ -0,0 +1,74 @@
+; RUN: llc -mtriple=i686-unknown-nacl -O0 -filetype=asm %s -o - | FileCheck %s \
+; RUN:   --check-prefix=NACL32
+; RUN: llc -mtriple=i686-unknown-nacl -filetype=asm %s -o - | FileCheck %s \
+; RUN:   --check-prefix=NACL32
+; RUN: llc -mtriple=x86_64-unknown-nacl -O0 -filetype=asm %s -o - | \
+; RUN:   FileCheck %s --check-prefix=NACL64
+; RUN: llc -mtriple=x86_64-unknown-nacl -filetype=asm %s -o - | \
+; RUN:   FileCheck %s --check-prefix=NACL64
+
+; Test that various bit manipulation intrinsics are supported by the
+; NaCl X86-32 and X86-64 backends.
+
+declare i16 @llvm.bswap.i16(i16)
+declare i32 @llvm.bswap.i32(i32)
+declare i64 @llvm.bswap.i64(i64)
+
+; NACL32: test_bswap_16
+; NACL32: rolw $8, %{{.*}}
+; NACL64: test_bswap_16
+; NACL64: rolw $8, %{{.*}}
+define i16 @test_bswap_16(i16 %a) {
+  %b = call i16 @llvm.bswap.i16(i16 %a)
+  ret i16 %b
+}
+
+; NACL32: test_bswap_const_16
+; NACL32: movw $-12885, %ax # imm = 0xFFFFFFFFFFFFCDAB
+; NACL64: test_bswap_const_16
+; NACL64: movw $-12885, %ax # imm = 0xFFFFFFFFFFFFCDAB
+define i16 @test_bswap_const_16() {
+  ; 0xabcd
+  %a = call i16 @llvm.bswap.i16(i16 43981)
+  ret i16 %a
+}
+
+; NACL32: test_bswap_32
+; NACL32: bswapl %eax
+; NACL64: test_bswap_32
+; NACL64: bswapl %edi
+define i32 @test_bswap_32(i32 %a) {
+  %b = call i32 @llvm.bswap.i32(i32 %a)
+  ret i32 %b
+}
+
+; NACL32: test_bswap_const_32
+; NACL32: movl $32492971, %eax # imm = 0x1EFCDAB
+; NACL64: test_bswap_const_32
+; NACL64: movl $32492971, %eax # imm = 0x1EFCDAB
+define i32 @test_bswap_const_32() {
+  ; 0xabcdef01
+  %a = call i32 @llvm.bswap.i32(i32 2882400001)
+  ret i32 %a
+}
+
+; NACL32: test_bswap_64
+; NACL32: bswapl %e{{.*}}
+; NACL32: bswapl %e{{.*}}
+; NACL64: test_bswap_64
+; NACL64: bswapq %rdi
+define i64 @test_bswap_64(i64 %a) {
+  %b = call i64 @llvm.bswap.i64(i64 %a)
+  ret i64 %b
+}
+
+; NACL32: test_bswap_const_64
+; NACL32: movl $32492971, %eax # imm = 0x1EFCDAB
+; NACL32: movl $-1989720797, %edx # imm = 0xFFFFFFFF89674523
+; NACL64: test_bswap_const_64
+; NACL64: movabsq	$-8545785751253561941, %rax # imm = 0x8967452301EFCDAB
+define i64 @test_bswap_const_64(i64 %a) {
+  ; 0xabcdef01 23456789
+  %b = call i64 @llvm.bswap.i64(i64 12379813738877118345)
+  ret i64 %b
+}