diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 23:30:25 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 23:30:25 +0000 |
| commit | 103bf951a4d221a9cff4a5a4766754cf0cb126f4 (patch) | |
| tree | 9ada412b5f1ab3715ccd248b87955c4f9629f12d | |
| parent | 6da3fe68c6e3f5abd520a1bfc8dd8429e6ec6389 (diff) | |
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 1 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-MOVr-arm.txt | 13 |
2 files changed, 14 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 28b53ca67c..f7182c397d 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1983,6 +1983,7 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, bits<4> Rd; bits<4> Rm; + let Inst{19-16} = 0b0000; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let Inst{3-0} = Rm; diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt new file mode 100644 index 0000000000..f82d3cb0b1 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.97 MOV (register) +0x2 0xd0 0xbc 0xf1 |