diff options
| author | Andrew Trick <atrick@apple.com> | 2012-03-16 05:04:25 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-03-16 05:04:25 +0000 |
| commit | d3a7486ef351697450cfe87b6cce82a3eb906874 (patch) | |
| tree | 5237cf0a4c61b1850af47d66a768a337ec477e39 | |
| parent | 75ae20366fd1b480f4cc38400bb075c43c9f4f7f (diff) | |
misched: add DAG edges from vreg defs to ExitSU.
These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152895 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 54828e28d1..1c455b95ab 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -201,8 +201,10 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() { if (TRI->isPhysicalRegister(Reg)) Uses[Reg].push_back(&ExitSU); - else + else { assert(!IsPostRA && "Virtual register encountered after regalloc."); + addVRegUseDeps(&ExitSU, i); + } } } else { // For others, e.g. fallthrough, conditional branch, assume the exit |