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authorEvan Cheng <evan.cheng@apple.com>2007-01-31 18:29:27 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-01-31 18:29:27 +0000
commita9b8b8d62c67e96bc4dc2ed25298c539102f8638 (patch)
treea346459625ce4694563a57af5fafdfc4a4807feb
parent934536dab2585079d72b0218b3d5a2ea07795beb (diff)
Some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33707 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMConstantIslandPass.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 32f8e8cb25..834b23f7e8 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -420,6 +420,7 @@ MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
// Add an unconditional branch from OrigBB to NewBB.
+ // Note the new unconditional branch is not being recorded.
BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB);
NumSplit++;
@@ -498,6 +499,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, CPUser &U){
assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
NewMBB = next(MachineFunction::iterator(UserMBB));
// Add an unconditional branch from UserMBB to fallthrough block.
+ // Note the new unconditional branch is not being recorded.
BuildMI(UserMBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewMBB);
BBSizes[UserMBB->getNumber()] += isThumb ? 2 : 4;
} else {
@@ -590,7 +592,9 @@ ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &Fn, ImmBranch &Br) {
return true;
}
-static inline unsigned getUncondBranchDisp(int Opc) {
+/// getUnconditionalBrDisp - Returns the maximum displacement that can fit in the
+/// specific unconditional branch instruction.
+static inline unsigned getUnconditionalBrDisp(int Opc) {
return (Opc == ARM::tB) ? (1<<10)*2 : (1<<23)*4;
}
@@ -653,7 +657,7 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB).addImm(CC);
Br.MI = &MBB->back();
BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
- unsigned MaxDisp = getUncondBranchDisp(Br.UncondBr);
+ unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
MI->eraseFromParent();