Make sret register classes match for llc at -O0.

PointerTy() is i32, so we end up with EDI as the sret
register.  However, this means that the copy to RAX won't
match.  We could either copy to EAX to have the register
classes match, or promote EDI to RDI then copy.
It shouldn't matter much since only the lower 32-bits matter.
The EDI -> EAX version is 2 bytes while the the
RDI -> RAX version is 3 bytes, so let's pick the smaller one.

Also augment existing test to tickle the NaCl triple.

This is mostly to get the debugger test working (since the
debugger test fails when optimization is turned on).

BUG= http://code.google.com/p/nativeclient/issues/detail?id=3104
BUG= http://code.google.com/p/nativeclient/issues/detail?id=2544

TEST= ./scons bitcode=1 platform=x86-64 run_gdb_change_variable_test (with a hacked driver that use -O0 for llc)
TEST= test/CodeGen/X86/fast-isel-x86-64.ll

Review URL: https://codereview.chromium.org/11308022

2 files changed, 15 insertions, 2 deletions

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index b8f7a6881f..a5285d4dd8 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -833,9 +833,16 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
     unsigned Reg = X86MFInfo->getSRetReturnReg();
     assert(Reg &&
            "SRetReturnReg should have been set in LowerFormalArguments()!");
+    // @LOCALMOD-BEGIN -- Ensure that the register classes match.
+    // At this point, SRetReturnReg is EDI, because PointerTy() for NaCl
+    // is i32.  We then copy to EAX instead of RAX.  Alternatively, we could
+    // have zero-extended EDI to RDI then copy to RAX, but this has a smaller
+    // encoding (2 bytes vs 3 bytes).
+    unsigned CopyTo = Subtarget->has64BitPointers() ? X86::RAX : X86::EAX;
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
-            X86::RAX).addReg(Reg);
-    MRI.addLiveOut(X86::RAX);
+            CopyTo).addReg(Reg);
+    MRI.addLiveOut(CopyTo);
+    // @LOCALMOD-END
   }
 
   // Now emit the RET.
diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll
index cdfaf7f4c1..4800743a5f 100644
--- a/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -mattr=-avx -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s
 ; RUN: llc < %s -mattr=+avx -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort -mtriple=x86_64-none-nacl | FileCheck %s --check-prefix=NACL64
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
@@ -301,6 +302,11 @@ define void @test23(i8* noalias sret %result) {
 ; CHECK: call
 ; CHECK: movq  %rdi, %rax
 ; CHECK: ret
+; NACL64: test23:
+; NACL64: call
+; NACL64: movl  %edi, %eax
+; NACL64: popq %rcx
+; NACL64: nacljmp %ecx, %r15
 }
 
 declare i8* @foo23()