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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-10 20:49:18 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-10 20:49:18 +0000 |
| commit | 53642c533564c41d9a85ad28efe19b12fc2305ce (patch) | |
| tree | a01b29fa9b7e01671dfd22fefa38f960b744f051 | |
| parent | 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 (diff) | |
Fix typo. Not quite sure how that slipped in there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 8273ffc44a..fcc8a6a7fd 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -2740,9 +2740,9 @@ validateInstruction(MCInst &Inst, "destination operands must be sequential"); return false; } - case ARM::STRgD: - case ARM::STRgD_PRE: - case ARM::STRgD_POST: + case ARM::STRD: + case ARM::STRD_PRE: + case ARM::STRD_POST: case ARM::STREXD: { // Rt2 must be Rt + 1. unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); |