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| author | Bob Wilson <bob.wilson@apple.com> | 2010-08-14 03:18:29 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-08-14 03:18:29 +0000 |
| commit | 136e4912806a2182a41e3011e86830a9c77160f0 (patch) | |
| tree | a939babc54d286bf5ee4133568901b3305cda4fc | |
| parent | 865287de4a93b9906bcfb2d57b66c32ed1fd870c (diff) | |
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 16b7cb41f3..1e8d80aed2 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -275,7 +275,7 @@ multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { // register def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, opc, "\t$dst, $rhs, $lhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { + [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = opcod; |