aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeter Collingbourne <peter@pcc.me.uk>2011-04-29 18:47:25 +0000
committerPeter Collingbourne <peter@pcc.me.uk>2011-04-29 18:47:25 +0000
commit8a70192b510e2a0f05493b9212e998017f3d178d (patch)
tree51617ac863e94c5d1b82f54b32f80c90ad714f75
parentc8497b6a2565046b5e6b5f2ea9dedc62b53dd966 (diff)
SimplifyCFG: Add Trunc, ZExt and SExt to the list of cheap instructions for phi node folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130526 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Transforms/Utils/SimplifyCFG.cpp3
-rw-r--r--test/Transforms/SimplifyCFG/PhiEliminate2.ll15
2 files changed, 12 insertions, 6 deletions
diff --git a/lib/Transforms/Utils/SimplifyCFG.cpp b/lib/Transforms/Utils/SimplifyCFG.cpp
index 5177d33959..1bddecb8c4 100644
--- a/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -261,6 +261,9 @@ static bool DominatesMergePoint(Value *V, BasicBlock *BB,
case Instruction::LShr:
case Instruction::AShr:
case Instruction::ICmp:
+ case Instruction::Trunc:
+ case Instruction::ZExt:
+ case Instruction::SExt:
break; // These are all cheap and non-trapping instructions.
}
diff --git a/test/Transforms/SimplifyCFG/PhiEliminate2.ll b/test/Transforms/SimplifyCFG/PhiEliminate2.ll
index c0f6781293..0b3893d520 100644
--- a/test/Transforms/SimplifyCFG/PhiEliminate2.ll
+++ b/test/Transforms/SimplifyCFG/PhiEliminate2.ll
@@ -1,14 +1,17 @@
; RUN: opt < %s -simplifycfg -S | not grep br
-define i32 @test(i1 %C, i32 %V1, i32 %V2) {
+define i32 @test(i1 %C, i32 %V1, i32 %V2, i16 %V3) {
entry:
- br i1 %C, label %then, label %Cont
+ br i1 %C, label %then, label %else
then: ; preds = %entry
- %V3 = or i32 %V2, %V1 ; <i32> [#uses=1]
+ %V4 = or i32 %V2, %V1 ; <i32> [#uses=1]
br label %Cont
-Cont: ; preds = %then, %entry
- %V4 = phi i32 [ %V1, %entry ], [ %V3, %then ] ; <i32> [#uses=0]
- call i32 @test( i1 false, i32 0, i32 0 ) ; <i32>:0 [#uses=0]
+else: ; preds = %entry
+ %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1]
+ br label %Cont
+Cont: ; preds = %then, %else
+ %V6 = phi i32 [ %V5, %else ], [ %V4, %then ] ; <i32> [#uses=0]
+ call i32 @test( i1 false, i32 0, i32 0, i16 0 ) ; <i32>:0 [#uses=0]
ret i32 %V1
}