diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 20:21:38 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-01 20:21:38 +0000 |
| commit | ec30f6f5e5e53f384f3cbdade08ba654ef3680c7 (patch) | |
| tree | 4d5c524d79d9248065d099488d9240e545a4d281 | |
| parent | ce1498bdbe32d0d6ab14d449d559ee76c0b30d9d (diff) | |
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 3 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDRT-arm.txt | 12 |
3 files changed, 23 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index c28f7e12ef..884a056ef5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1106,6 +1106,14 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn, MI.addOperand(MCOperand::CreateImm(Offset)); OpIdx += 1; } else { + // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of + // A8.6.86 LDRT. So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1, + // we should reject this insn as invalid. + // + // Ditto for LDRBT. + if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1)) + return false; + // Disassemble the offset reg (Rm), shift type, and immediate shift length. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 7947c6a3d5..4e39e8e9b3 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -45,6 +45,9 @@ # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 +# CHECK: ldr r5, [r7, -r10, lsl #2] +0x0a 0x51 0x17 0xe7 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt new file mode 100644 index 0000000000..fb2ce20d2c --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. +0x10 0x51 0x37 0xe6 + + |