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authorVikram S. Adve <vadve@cs.uiuc.edu>2002-03-18 03:18:28 +0000
committerVikram S. Adve <vadve@cs.uiuc.edu>2002-03-18 03:18:28 +0000
commit80347ecb148534169086c719c8228e4e03bdce96 (patch)
tree9ef799d5a102fd6462dcd1062aba7d729d05b29e
parent7482532129d8f181f4d826a7362d500310db32b0 (diff)
Add function getRegClassIDOfType.
getRegClassIDOfValue is now just a wrapper around this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1897 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/Target/TargetRegInfo.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index 5f88ae9e83..9b787bb553 100644
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -14,6 +14,7 @@
class TargetMachine;
class IGNode;
+class Type;
class Value;
class LiveRangeInfo;
class Method;
@@ -84,9 +85,11 @@ public:
// condition code register. If isCCReg is true below, the ID of the condition
// code regiter class will be returned. Otherwise, the normal register
// class (eg. int, float) must be returned.
+ virtual unsigned getRegClassIDOfType (const Type *type,
+ bool isCCReg = false) const =0;
virtual unsigned getRegClassIDOfValue (const Value *Val,
bool isCCReg = false) const =0;
-
+
inline unsigned int getNumOfRegClasses() const {
return MachineRegClassArr.size();