Add RIP to getX86SubSuperRegister

The change to getX86SubSuperRegister avoids the assertion failures caused by LLVM r164919, and can perhaps be reverted when LEA-related fixes to the td files are made.
The change to the nacl rewrite pass are required to avoid a more direct triggering of the assert, and can stay regardless.

BUG=

Review URL: https://codereview.chromium.org/11028151

2 files changed, 11 insertions, 2 deletions

diff --git a/lib/Target/X86/X86NaClRewritePass.cpp b/lib/Target/X86/X86NaClRewritePass.cpp
index 0d1381c8b0..fcc5a4bf8d 100644
--- a/lib/Target/X86/X86NaClRewritePass.cpp
+++ b/lib/Target/X86/X86NaClRewritePass.cpp
@@ -139,8 +139,7 @@ static bool IsRegAbsolute(unsigned Reg) {
   const bool RestrictR15 = FlagRestrictR15;
   assert(UseZeroBasedSandbox || RestrictR15);
   return (Reg == X86::RSP || Reg == X86::RBP ||
-          (Reg == X86::R15 && RestrictR15) ||
-          Reg == X86::RIP);
+          (Reg == X86::R15 && RestrictR15));
 }
 
 static bool FindMemoryOperand(const MachineInstr &MI, unsigned* index) {
@@ -521,6 +520,10 @@ bool X86NaClRewritePass::ApplyMemorySFI(MachineBasicBlock &MBB,
   //MachineOperand &Disp = MI.getOperand(MemOp + 3);
   MachineOperand &SegmentReg = MI.getOperand(MemOp + 4);
 
+  // RIP-relative addressing is safe.
+  if (BaseReg.getReg() == X86::RIP)
+    return false;
+
   // Make sure the base and index are 64-bit registers.
   IndexReg.setReg(PromoteRegTo64(IndexReg.getReg()));
   BaseReg.setReg(PromoteRegTo64(BaseReg.getReg()));
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 262d32e4e6..18101ad6b1 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -738,6 +738,9 @@ unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
       return X86::R14D;
     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
       return X86::R15D;
+    // @LOCALMOD. TODO: possibly revert this after LEA .td fixes
+    case X86::EIP: case X86::RIP:
+      return X86::EIP;
     }
   case MVT::i64:
     // For 64-bit mode if we've requested a "high" register and the
@@ -790,6 +793,9 @@ unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
       return X86::R14;
     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
       return X86::R15;
+    // @LOCALMOD. TODO: possibly revert this after LEA .td fixes
+    case X86::EIP: case X86::RIP:
+      return X86::RIP;
     }
   }
 }