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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-07 23:14:41 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-07 23:14:41 +0000 |
| commit | 0a18cdc372a4ca1bd685071d99016ad57ba9d77e (patch) | |
| tree | 92b8d0b7f133942db0ed8d647af37b88aca1df89 | |
| parent | 9fa0a743e6afef4ea5fe7b5115607947696774a8 (diff) | |
32 to 64-bit zext pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/mips64ext.ll | 11 |
2 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index bc9c5602ca..91c91022fd 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -222,6 +222,9 @@ def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, def DEXT : ExtBase<3, "dext", CPU64Regs>; def DINS : InsBase<7, "dins", CPU64Regs>; +def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), + "dsll32\t$rd, $rt, 0", [], IIAlu>; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// @@ -296,3 +299,5 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>; def : Pat<(i32 (trunc CPU64Regs:$src)), (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>; +// 32-to-64-bit extension +def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>; diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll new file mode 100644 index 0000000000..33af0d852d --- /dev/null +++ b/test/CodeGen/Mips/mips64ext.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s + +define i64 @zext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2 +; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0 +; CHECK: dsrl32 ${{[0-9]+}}, $[[R1]], 0 + %add = add i32 %a, 2 + %conv = zext i32 %add to i64 + ret i64 %conv +} |