aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBob Wilson <bob.wilson@apple.com>2009-08-31 21:54:16 +0000
committerBob Wilson <bob.wilson@apple.com>2009-08-31 21:54:16 +0000
commitd4034b2825a2a030893593327d67ca12b4e8a249 (patch)
tree622a7b304f6113f33cc3dfb23470d91ad10e3329
parent768f1dd48fbc1582213271f2698a0328d03d4d7e (diff)
If the tied registers are already the same, there is no need to change
them. Move the code to make that change inside the conditional. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80630 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 738b3c97ac..d8871f98ac 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -985,13 +985,13 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi->getOperand(i).getReg() == regB)
mi->getOperand(i).setReg(regA);
}
- }
- assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
- mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
- MadeChange = true;
+ assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
+ mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
+ MadeChange = true;
- DEBUG(errs() << "\t\trewrite to:\t" << *mi);
+ DEBUG(errs() << "\t\trewrite to:\t" << *mi);
+ }
}
mi = nmi;